ADD

Add

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX.W + 03 /r ADD r64, r/m64 A Valid N.E. Add r/m64 to r64.
03 /r ADD r32, r/m32 A Valid Valid Add r/m32 to r32.
03 /r ADD r16, r/m16 A Valid Valid Add r/m16 to r16.
REX + 02 /r ADD r8*, r/m8* A Valid N.E. Add r/m8 to r8.
02 /r ADD r8, r/m8 A Valid Valid Add r/m8 to r8.
REX.W + 01 /r ADD r/m64, r64 A Valid N.E. Add r64 to r/m64.
01 /r ADD r/m32, r32 A Valid Valid Add r32 to r/m32.
01 /r ADD r/m16, r16 A Valid Valid Add r16 to r/m16.
REX + 00 /r ADD r/m8*, r8* A Valid N.E. Add r8 to r/m8.
00 /r ADD r/m8, r8 A Valid Valid Add r8 to r/m8.
REX.W + 83 /0 ib ADD r/m64, imm8 B Valid N.E. Add sign-extended imm8 to r/m64.
83 /0 ib ADD r/m32, imm8 B Valid Valid Add sign-extended imm8 to r/m32.
83 /0 ib ADD r/m16, imm8 B Valid Valid Add sign-extended imm8 to r/m16.
REX.W + 81 /0 id ADD r/m64, imm32 B Valid N.E. Add imm32 sign-extended to 64-bits to r/m64.
81 /0 id ADD r/m32, imm32 B Valid Valid Add imm32 to r/m32.
81 /0 iw ADD r/m16, imm16 B Valid Valid Add imm16 to r/m16.
REX + 80 /0 ib ADD r/m8 *, imm8 B Valid N.E. Add sign-extended imm8 to r/m64.
80 /0 ib ADD r/m8, imm8 B Valid Valid Add imm8 to r/m8.
REX.W + 05 id ADD RAX, imm32 C Valid N.E. Add imm32 sign-extended to 64-bits to RAX.
05 id ADD EAX, imm32 C Valid Valid Add imm32 to EAX.
05 iw ADD AX, imm16 C Valid Valid Add imm16 to AX.
04 ib ADD AL, imm8 C Valid Valid Add imm8 to AL.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)
B NA NA imm8 ModRM:r/m (r, w)
C NA NA imm8 AL/AX/EAX/RAX

Description

Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

DEST = DEST + SRC;

Flags Affected

The OF, SF, ZF, AF, CF, and PF flags are set according to the result.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.