ADDSUBPD

Packed Double-FP Add/Subtract

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F D0 /r ADDSUBPD xmm1, xmm2/m128 A Valid Valid Add/subtract doubleprecision floating-point values from xmm2/m128 to xmm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand.

Subtracts the double-precision floating-point value in the low quadword of the source operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand.

The source operand can be a 128-bit memory location or an XMM register. The destination operand is an XMM register.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

xmm1[63:0] = xmm1[63:0] -xmm2/m128[63:0];
xmm1[127:64] = xmm1[127:64] + xmm2/m128[127:64];

Exceptions

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Exceptions

When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

64-Bit Mode Exceptions

Exception Description
#UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
#UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#XM For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric excep tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#XM For an unmasked Streaming SIMD Extensions numeric excep tion, CR4.OSXMMEXCPT[bit 10] = 1.
#NM If TS bit in CR0 is 1.
#GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Protected Mode Exceptions

Exception Description
#UD If CR0.EM is 1. For an unmasked Streaming SIMD Extensions numeric excep tion (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#XM For an unmasked Streaming SIMD Extensions numeric excep tion, CR4.OSXMMEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.