BLENDVPD

Variable Blend Packed Double Precision Floating-Point Values

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 38 15 /r BLENDVPD xmm1, xmm2/m128 , A Valid Valid Select packed DP FP values from xmm1 and xmm2 from mask specified in XMM0 and store the values in xmm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA implicit XMM0 ModRM:r/m (r) ModRM:reg (r, w)

Description

Packed double-precision floating-point values from the source operand (second argument) are conditionally copied to the destination operand (first argument) depending on the mask bits in the implicit third register argument, XMM0. The mask bits are the most significant bit in each qword element of XMM0. Each mask bit corresponds to a quadword element in a 128-bit operand.

If a mask bit is "1", then the corresponding quadword element in the source operand is copied to the destination, else the quadword element in the destination operand is left unchanged.

The register assignment of the third operand is defined to be the architectural register XMM0.

Pseudo Code

MASK = XMM0;
IF (MASK[63] = 1)
	DEST[63:0] = SRC[63:0];
ELSE
	DEST[63:0] = DEST[63:0];
FI;
IF (MASK[127] = 1)
	DEST[127:64] = SRC[127:64];
ELSE
	DEST[127:64] = DEST[127:64];
FI;

Exceptions

SIMD Floating-Point Exceptions

None

64-Bit Mode Exceptions

Exception Description
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#GP(0) If the memory address is in a non-canonical form. INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If a memory address referencing the SS segment is in a non-canonical form. For a page fault. If TS in CR0 is set.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) if any part of the operand lies outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Protected Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.