CLTS

Clear Task-Switched Flag in CR0

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F 06 CLTS A Valid Valid Clears TS flag in CR0.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA NA NA

Description

Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.

The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU context in multitasking applications. See the description of the TS flag in the section titled "Control Registers" in Chapter 2 of theIntel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information about this flag.

CLTS operation is the same in non-64-bit modes and 64-bit mode.

See Chapter 22, "VMX Non-Root Operation," of theIntel®64 and IA-32 ArchitecturesSoftware Developer's Manual, Volume 3B, for more information about the behavior of this instruction in VMX non-root operation.

Pseudo Code

CR0.TS[bit 3] = 0;

Flags Affected

The TS flag in CR0 register is cleared.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) If the CPL is greater than 0.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) CLTS is not recognized in virtual-8086 mode.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) If the current privilege level is not 0.