CMOVcc

Conditional Move

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX.W + 0F 4F /r CMOVG r64, r/m64 A Valid N.E. Move if greater (ZF=0 and SF=OF).
0F 4F /r CMOVG r32, r/m32 A Valid Valid Move if greater (ZF=0 and SF=OF).
0F 4F /r CMOVG r16, r/m16 A Valid Valid Move if greater (ZF=0 and SF=OF).
REX.W + 0F 44 /r CMOVE r64, r/m64 A Valid N.E. Move if equal (ZF=1).
0F 44 /r CMOVE r32, r/m32 A Valid Valid Move if equal (ZF=1).
0F 44 /r CMOVE r16, r/m16 A Valid Valid Move if equal (ZF=1).
REX.W + 0F 42 /r CMOVC r64, r/m64 A Valid N.E. Move if carry (CF=1).
0F 42 /r CMOVC r32, r/m32 A Valid Valid Move if carry (CF=1).
0F 42 /r CMOVC r16, r/m16 A Valid Valid Move if carry (CF=1).
REX.W + 0F 46 /r CMOVBE r64, r/m64 A Valid N.E. Move if below or equal (CF=1 or ZF=1).
0F 46 /r CMOVBE r32, r/m32 A Valid Valid Move if below or equal (CF=1 or ZF=1).
0F 46 /r CMOVBE r16, r/m16 A Valid Valid Move if below or equal (CF=1 or ZF=1).
REX.W + 0F 42 /r CMOVB r64, r/m64 A Valid N.E. Move if below (CF=1).
0F 42 /r CMOVB r32, r/m32 A Valid Valid Move if below (CF=1).
0F 42 /r CMOVB r16, r/m16 A Valid Valid Move if below (CF=1).
REX.W + 0F 43 /r CMOVAE r64, r/m64 A Valid N.E. Move if above or equal (CF=0).
0F 43 /r CMOVAE r32, r/m32 A Valid Valid Move if above or equal (CF=0).
0F 43 /r CMOVAE r16, r/m16 A Valid Valid Move if above or equal (CF=0).
REX.W + 0F 47 /r CMOVA r64, r/m64 A Valid N.E. Move if above (CF=0 and ZF=0).
0F 47 /r CMOVA r32, r/m32 A Valid Valid Move if above (CF=0 and ZF=0).
0F 47 /r CMOVA r16, r/m16 A Valid Valid Move if above (CF=0 and ZF=0).

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

The CMOVcc instructions check the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and perform a move operation if the flags are in a specified state (or condition). A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, a move is not performed and execution continues with the instruction following the CMOVcc instruction.

These instructions can move 16-bit, 32-bit or 64-bit values from memory to a general-purpose register or from one general-purpose register to another. Conditional moves of 8-bit register operands are not supported.

The condition for each CMOVcc mnemonic is given in the description column of the above table. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the CMOVA (conditional move if above) instruction and the CMOVNBE (conditional move if not below or equal) instruction are alternate mnemonics for the opcode 0F 47H.

The CMOVcc instructions were introduced in P6 family processors; however, these instructions may not be supported by all IA-32 processors. Software can determine if the CMOVcc instructions are supported by checking the processor's feature information with the CPUID instruction (see "CPUID—CPU Identification" in this chapter).

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

temp = SRC
IF condition TRUE
	DEST = temp;
ELSE
	IF (OperandSize = 32 and IA-32e mode active)
		DEST[63:32] = 0;
	FI;
FI;

Flags Affected

None.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.