CMP

Compare Two Operands

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
81 /7 id CMP r/m32, imm32 C Valid Valid Compare imm32 with r/m32.
81 /7 iw CMP r/m16, imm16 C Valid Valid Compare imm16 with r/m16.
REX + 80 /7 ib CMP r/m8 *, imm8 C Valid N.E. Compare imm8 with r/m8.
80 /7 ib CMP r/m8, imm8 C Valid Valid Compare imm8 with r/m8.
REX.W + 3D id CMP RAX, imm32 D Valid N.E. Compare imm32 sign-extended to 64-bits with RAX.
3D id CMP EAX, imm32 D Valid Valid Compare imm32 with EAX.
3D iw CMP AX, imm16 D Valid Valid Compare imm16 with AX.
3C ib CMP AL, imm8 D Valid Valid Compare imm8 with AL.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)
B NA NA ModRM:reg (w) ModRM:r/m (r, w)
C NA NA imm8 ModRM:r/m (r, w)
D NA NA imm8 AL/AX/EAX/RAX

Description

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand.

The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction. Appendix B, "EFLAGS Condition Codes," in theIntel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1, shows the relationship of the status flags and the condition codes.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

temp = SRC1 - SignExtend(SRC2);
ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction *)

Flags Affected

The CF, OF, SF, ZF, AF, and PF flags are set according to the result.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.