CMPPD

Compare Packed Double-Precision Floating-Point Values

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F C2 /r ib CMPPD xmm1, xmm2/m128, imm8 A Valid Valid Compare packed doubleprecision floating-point values in xmm2/m128 and xmm1 using imm8 as comparison predicate.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a SIMD compare of the two packed double-precision floating-point values in the source operand (second operand) and the destination operand (first operand) and returns the results of the comparison to the destination operand. The comparison predicate operand (third operand) specifies the type of comparison performed on each of the pairs of packed values. The result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The comparison predicate operand is an 8-bit immediate, the first 3 bits of which define the type of comparison to be made (see "Comparison Predicate for CMPPD and CMPPS Instructions"). Bits 3 through 7 of the immediate are reserved.

"Comparison Predicate for CMPPD and CMPPS Instructions". Comparison Predicate for CMPPD and CMPPS Instructions

Predicate imm8 Encoding Description Relation where: A Is 1st Operand B Is 2nd Operand Emulation Result if NaN Operand QNaN Oper-and Signals Invalid
EQ 000B Equal A = B False No
LT 001B Less-than A < B False Yes
LE 010B Less-than-or-equal A &le B False Yes
Greater than A > B Swap Operands, Use LT False Yes
Greater-than-orequal A &ge B Swap Operands, Use LE False Yes
UNORD 011B Unordered A, B = Unordered True No
NEQ 100B Not-equal A != B True No
NLT 101B Not-less-than NOT(A < B) True Yes
NLE 110B Not-less-than-orequal NOT(A &le B) True Yes
Not-greater-than NOT(A > B) Swap Operands, Use NLT True Yes
Not-greater-thanor-equal NOT(A &ge B) Swap Operands, Use NLE True Yes
ORD 111B Ordered A , B = Ordered False No

The unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN.

A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN.

Note that the processor does not implement the greater-than, greater-than-orequal, not-greater-than, and not-greater-than-or-equal relations. These comparisons can be made either by using the inverse relationship (that is, use the "not-lessthan-or-equal" to make a "greater-than" comparison) or by using software emulation. When using software emulation, the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in "Comparison Predicate for CMPPD and CMPPS Instructions" under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPD instruction. See "Comparison Predicate for CMPPD and CMPPS Instructions".

: Table 3-8. Pseudo-Op and CMPPD Implementation Table 3-8. Pseudo-Op and CMPPD Implementation

Pseudo-Op CMPPD Implementation
CMPEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 0
CMPLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 1
CMPLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 2
CMPUNORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 3
CMPNEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 4
CMPNLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 5
CMPNLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 6
CMPORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 7

The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.)

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

CASE (COMPARISON PREDICATE) OF
	0: OP = EQ;
	1: OP = LT;
	2: OP = LE;
	3: OP = UNORD;
	4: OP = NEQ;
	5: OP = NLT;
	6: OP = NLE;
	7: OP = ORD;
	DEFAULT: Reserved;
	CMP0 = DEST[63:0] OP SRC[63:0];
	CMP1 = DEST[127:64] OP SRC[127:64];
	IF CMP0 = TRUE
		DEST[63:0] = FFFFFFFFFFFFFFFFH;
	ELSE
		DEST[63:0] = 0000000000000000H;
	FI;
	IF CMP1 = TRUE
		DEST[127:64] = FFFFFFFFFFFFFFFFH;
	ELSE
		DEST[127:64] = 0000000000000000H;
	FI;
ESAC;

Exceptions

SIMD Floating-Point Exceptions

Invalid if SNaN operand and invalid if QNaN and predicate as listed in above table, Denormal.

64-Bit Mode Exceptions

Exception Description
#UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#UD If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#UD If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.