CPUID

CPU Identification

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F A2 CPUID A Valid Valid Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (in some cases, ECX as well).

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA NA NA

Description

The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode.

CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes. The instruction's output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well). For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value and the Vendor Identification String in the appropriate registers:

MOV EAX, 00H
CPUID

"Information Returned by CPUID Instruction" shows information returned, depending on the initial value loaded into the EAX register. Table 3-13 shows the maximum CPUID input value recognized for eachfamily of IA-32 processors on which CPUID is implemented.

Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX is higher than the maximum input value for basic or extended function for that processor then the data for the highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:

CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)
CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)

If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on that processor then 0 is returned in all the registers. For example, using the Intel Core i7 processor, the following is true:

CPUID.EAX = 07H (* Returns EAX=EBX=ECX=EDX=0. *)

When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence on input ECX value in the basic leaf is honored.

CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed.

Information Returned by CPUID Instruction
Initial EAX Value Information Provided about the Processor
0H

Basic CPUID Information:

EAX Maximum Input Value for Basic CPUID Information (see Table 3-13)
EBX "Genu"
ECX "ntel"
EDX "ineI"
01H
EAX Version Information: Type, Family, Model, and Stepping ID (see Figure 3-5)
EBX Bits 7-0: Brand Index
Bits 15-8: CLFLUSH line size (Value * 8 = cache line size in bytes)
Bits 23-16: Maximum number of addressable IDs for logical processors in this physical package*.
Bits 31-24: Initial APIC ID
ECX Feature Information (see Figure 3-6 and Table 3-15)
EDX Feature Information (see Figure 3-7 and Table 3-16)
  • Notes:
  • * The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.
02H
EAX Cache and TLB Information (see Table 3-17)
EBX Cache and TLB Information
ECX Cache and TLB Information
EDX Cache and TLB Information
03H
EAX Reserved.
EBX Reserved.
ECX Bits 00-31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)
EDX Bits 32-63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)
  • Notes:
  • Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.
  • See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) for more information on PSN.
  • CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
Deterministic Cache Parameters Leaf
04H
EAX
  • Bits 4-0: Cache Type Field
    • 0 = Null - No more caches
    • 1 = Data Cache
    • 2 = Instruction Cache
    • 3 = Unified Cache
    • 4-31 = Reserved Bits
  • 7-5: Cache Level (starts at 1)
  • Bits 8: Self Initializing cache level (does not need SW initialization)
  • Bits 9: Fully Associative cache
  • Bits 13-10: Reserved
  • Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache*, **
  • Bits 31-26: Maximum number of addressable IDs for processor cores in the physical package*, ***, ****
EBX Bits 11-00: L = System Coherency Line Size*
Bits 21-12: P = Physical Line partitions*
Bits 31-22: W = Ways of associativity*
ECX Bits 31-00: S = Number of Sets* Information Provided about the Processor
EDX
  • Bit 0: Write-Back Invalidate/Invalidate
    • 0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache.
    • 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.
  • Bit 1: Cache Inclusiveness
    • 0 = Cache is not inclusive of lower cache levels.
    • 1 = Cache is inclusive of lower cache levels.
  • Bit 2: Complex Cache Indexing
    • 0 = Direct mapped cache.
    • 1 = A complex function is used to index the cache, potentially using all address bits.
  • Bits 31-03: Reserved = 0
  • Notes:
  • Leaf 04H output depends on the initial value in ECX. See also: INPUT EAX = 4: Returns Deterministic Cache Parameters for each level on page 3-221.
  • * Add one to the return value to get the result.
  • ** The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache
  • *** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of bits of the initial APIC ID.
  • ****The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.
MONITOR/MWAIT Leaf
05H
EAX Bits 15-00: Smallest monitor-line size in bytes (default is processor's monitor granularity)
Bits 31-16: Reserved = 0
EBX Bits 15-00: Largest monitor-line size in bytes (default is processor's monitor granularity)
Bits 31-16: Reserved = 0
ECX Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported
Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled
Bits 31 - 02: Reserved Information Provided about the Processor
EDX Bits 03 - 00: Number of C0* sub C-states supported using MWAIT
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT
Bits 31 - 20: Reserved = 0
  • Notes:
  • * The definition of C0 through C4 states for MWAIT extension are processor-specific C-states, not ACPI C-states.
Thermal and Power Management Leaf
06H
EAX Bit 00: Digital temperature sensor is supported if set
Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLES[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved Bit
04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bits 31 - 07: Reserved
EBX Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor
Bits 31 - 04: Reserved
ECX Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of expected processor performance at frequency specified in CPUID Brand String
Bits 02 - 01: Reserved = 0
Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)
Bits 31 - 04: Reserved = 0
EDX Reserved = 0
Direct Cache Access Information Leaf
09H
EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H)
EBX Reserved
ECX Reserved
EDX Reserved
Architectural Performance Monitoring Leaf
0AH
EAX Bits 07 - 00: Version ID of architectural performance monitoring
Bits 15- 08: Number of general-purpose performance monitoring counter per logical processor
Bits 23 - 16: Bit width of general-purpose, performance monitoring counter
Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events
EBX Bit 0: Core cycle event not available if 1
Bit 1: Instruction retired event not available if 1
Bit 2: Reference cycles event not available if 1
Bit 3: Last-level cache reference event not available if 1
Bit 4: Last-level cache misses event not available if 1
Bit 5: Branch instruction retired event not available if 1
Bit 6: Branch mispredict retired event not available if 1
Bits 31- 07: Reserved = 0
ECX Reserved = 0
EDX Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1)
Bits 12- 05: Bit width of fixed-function performance counters (if Version ID > 1)
Reserved = 0
Extended Topology Enumeration Leaf
0BH
  • Notes:
  • Most of Leaf 0BH output depends on the initial value in ECX. EDX output do not vary with initial value in ECX. ECX[7:0] output always reflect initial value in ECX. All other output value for an invalid initial value in ECX are 0. Leaf 0BH exists if EBX[15:0] is not zero.
EAX Bits 4-0: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*. All logical processors with the same next level ID share current level.
Bits 31-5: Reserved.
EBX Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped by Intel**.
Bits 31- 16: Reserved.
ECX Bits 07 - 00: Level number. Same value in ECX input
Bits 15 - 08: Level type***.
Bits 31 - 16:: Reserved.
EDX Bits 31- 0: x2APIC ID the current logical processor. Information Provided about the Processor
  • Notes:
  • * Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
  • ** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and platform hardware configurations.
  • *** The value of the "level type" field is not related to level numbers in any way, higher "level type" values do not mean higher levels. Level type field has the following encoding:
    • 0 : invalid
    • 1 : SMT
    • 2 : Core
    • 3-255 : Reserved
Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)
0DH
  • Notes:
  • Leaf 0DH main leaf (ECX = 0).
EAX Bits 31-0: Reports the valid bit fields of the lower 32 bits of the XFEATURE_ENABLED_MASK register (XCR0). If a bit is 0, the corresponding bit field in XCR0 is reserved.
EBX Bits 31-0: Maximum size (bytes) required by enabled features in XFEATURE_ENABLED_MASK (XCR0). May be different than ECX when features at the end of the save area are not enabled.
ECX Bit 31-0: Maximum size (bytes) of the XSAVE/XRSTOR save area required by all supported features in the processor, i.e all the valid bit fields in XFEATURE_ENABLED_MASK. This includes the size needed for the XSAVE.HEADER.
EDX Bit 31-0: Reports the valid bit fields of the upper 32 bits of the XFEATURE_ENABLED_MASK register (XCR0). If a bit is 0, the corresponding bit field in XCR0 is reserved. Information Provided about the Processor
Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
EAX Reserved
EBX Reserved
ECX Reserved
EDX Reserved
Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
0DH
  • Notes:
  • Leaf 0DH output depends on the initial value in ECX.
  • If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0.
EAX Bits 31-0: The size in bytes of the save area for an extended state feature associated with a valid sub-leaf index, n. Each valid sub-leaf index maps to a valid bit in the XFEATURE_ENABLED_MASK register (XCR0) starting at bit position 2. This field reports 0 if the sub-leaf index, n, is invalid*.
EBX Bits 31-0: The offset in bytes of the save area from the beginning of the XSAVE/XRSTOR area. This field reports 0 if the sub-leaf index, n, is invalid*.
ECX This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
EDX This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
Unimplemented CPUID Leaf Functions
40000000H - 4FFFFFFFH Invalid. No existing or future CPU will return processor identification or feature information if the initial EAX value is in the range 40000000H to 4FFFFFFFH.
Extended Function CPUID Information
80000000H
EAX Maximum Input Value for Extended Function CPUID Information (see Table 3-13).
EBX Reserved
ECX Reserved
EDX Reserved
80000001H
EAX Extended Processor Signature and Feature Bits.
EBX Reserved
ECX Bit 0: LAHF/SAHF available in 64-bit mode
Bits 31-1 Reserved
EDX Bits 10-0: Reserved
Bit 11: SYSCALL/SYSRET available (when in 64-bit mode)
Bits 19-12: Reserved = 0
Bit 20: Execute Disable Bit available
Bits 25-21: Reserved = 0
Bit 26: 1-GByte pages are available if 1
Bit 27: RDTSCP and IA32_TSC_AUX are available if 1
Bits 28: Reserved = 0
Bit 29: Intel® 64 Architecture available if 1
Bits 31-30: Reserved = 0
80000002H
EAX Processor Brand String
EBX Processor Brand String Continued
ECX Processor Brand String Continued
EDX Processor Brand String Continued
80000003H
EAX Processor Brand String Continued
EBX Processor Brand String Continued
ECX Processor Brand String Continued
EDX Processor Brand String Continued
80000004H
EAX Processor Brand String Continued
EBX Processor Brand String Continued
ECX Processor Brand String Continued
EDX Processor Brand String Continued
80000005H
EAX Reserved = 0
EBX Reserved = 0
ECX Reserved = 0
EDX Reserved = 0
80000006H
EAX Reserved = 0
EBX Reserved = 0
ECX Bits 7-0: Cache Line size in bytes
Bits 15-12: L2 Associativity field *
Bits 31-16: Cache size in 1K units
EDX Reserved = 0 Information Provided about the Processor
  • Notes:
  • * L2 associativity field encodings:
    • 00H - Disabled
    • 01H - Direct mapped
    • 02H - 2-way
    • 04H - 4-way
    • 06H - 8-way
    • 08H - 16-way
    • 0FH - Fully associative
80000007H
EAX Reserved = 0
EBX Reserved = 0
ECX Reserved = 0
EDX Bits 7-0: Reserved = 0>/td>
Bit 8: Invariant TSC available if 1
Bits 31-9: Reserved = 0
80000008H
EAX Linear/Physical Address size
Bits 7-0: #Physical Address Bits*
Bits 15-8: #Linear Address Bits
Bits 31-16: Reserved = 0
EBX Reserved = 0
ECX Reserved = 0
  • Notes:
  • * If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should come from this field.

INPUT EAX = 0: Returns CPUID's Highest Value for Basic Processor Information and the Vendor Identification String

When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for returning basic processor information. The value is returned in the EAX register (see the following table) and is processor specific.

A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is "GenuineIntel" and is expressed:

INPUT EAX = 80000000H: Returns CPUID's Highest Value for Extended Processor Information

When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recognizes for returning extended processor information. The value is returned in the EAX register (see the following table) and is processor specific.

Highest CPUID Source Operand for Intel 64 and IA-32 Processors
Intel 64 or IA-32 Processors Highest Value in EAX
Basic Information Extended Function Information
Earlier Intel486 Processors CPUID Not Implemented CPUID Not Implemented
Later Intel486 Processors and Pentium Processors 01H Not Implemented
Pentium Pro and Pentium II Processors, Intel® Celeron® Processors 02H Not Implemented
Pentium III Processors 03H Not Implemented
Pentium 4 Processors 02H 80000004H
Intel Xeon Processors 02H 80000004H
Pentium M Processor 02H 80000004H
Pentium 4 Processor supporting Hyper-Threading Technology 05H 80000008H
Pentium D Processor (8xx) 05H 80000008H
Pentium D Processor (9xx) 06H 80000008H
Intel Core Duo Processor 0AH 80000008H
Intel Core 2 Duo Processor 0AH 80000008H
Intel Xeon Processor 3000, 5100, 5200, 5300, 5400 Series 0AH 80000008H
Intel Core 2 Duo Processor 8000 Series 0DH 80000008H
Intel Xeon Processor 5200, 5400 Series 0AH 80000008H
Intel Atom Processor 0AH 80000008H
Intel Core i7 Processor 0BH 80000008H

IA32_BIOS_SIGN_ID Returns Microcode Update Signature

For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in theIntel® 64 and IA-32Architectures Software Developer's Manual, Volume 3A.

INPUT EAX = 1: Returns Model, Family, Stepping Information

When CPUID executes with EAX set to 1, version information is returned in EAX (see Figure 3-5). For example: model, family, and processor type for the Intel Xeonprocessor 5100 series is as follows:

See the following for available processor type values. Stepping IDs are provided as needed.

Processor Type Field
Type Encoding
Original OEM Processor 00B
Intel OverDrive® Processor 01B
Dual processor (not applicable to Intel486 processors) 10B
Intel reserved 11B

The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display using the following rule:

IF Family_ID != 0FH
THEN DisplayFamily = Family_ID;
ELSE DisplayFamily = Extended_Family_ID + Family_ID;
(* Right justify and zero-extend 4-bit field. *)
FI;
(* Show DisplayFamily as HEX field. *)

The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a display using the following rule:

IF (Family_ID = 06H or Family_ID = 0FH)
THEN DisplayModel = (Extended_Model_ID << 4) + Model_ID;
(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)
ELSE DisplayModel = Model_ID;
FI;
(* Show DisplayModel as HEX field. *)

INPUT EAX = 1: Returns Additional Information in EBX

When CPUID executes with EAX set to 1, additional information is returned to the EBX register:

INPUT EAX = 1: Returns Feature Information in ECX and EDX

When CPUID executes with EAX set to 1, feature information is returned in ECX and EDX.

For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.

Important note

Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features.

Feature Information Returned in the ECX Register
Bit # Mnemonic Description
0 SSE3 Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology.
1 PCLMULQDQ PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction
2 DTES64 64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout
3 MONITOR MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.
4 DS-CPL CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL.
5 VMX Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology
6 SMX Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See Chapter 6, "Safer Mode Extensions Reference".
7 EST Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this technology.
8 TM2 Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.
9 SSSE3 A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor
10 CNXT-ID L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
11 Reserved Reserved
12 FMA A value of 1 indicates the processor supports FMA extensions using YMM state.
13 CMPXCHG16B CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the "CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes" section in this chapter for a description.
14 xTPR Update Control xTPR Update Control. A value of 1 indicates that the processor supports changing IA32_MISC_ENABLES[bit 23].
15 PDCM Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.
16 Reserved Reserved
17 PCID Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that software may set CR4.PCIDE to 1.
18 DCA A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device.
19 SSE4.1 A value of 1 indicates that the processor supports SSE4.1.
20 SSE4.2 A value of 1 indicates that the processor supports SSE4.2.
21 x2APIC A value of 1 indicates that the processor supports x2APIC feature.
22 MOVBE A value of 1 indicates that the processor supports MOVBE instruction.
23 POPCNT A value of 1 indicates that the processor supports the POPCNT instruction.
24 TSC-Deadline A value of 1 indicates that the processor's local APIC timer supports one-shot operation using a TSC deadline value.
25 AESNI A value of 1 indicates that the processor supports the AESNI instruction extensions.
26 XSAVE A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and the XFEATURE_ENABLED_MASK register (XCR0).
27 OSXSAVE A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions to access the XFEATURE_ENABLED_MASK register (XCR0), and support for processor extended state management using XSAVE/XRSTOR.
28 AVX A value of 1 indicates the processor supports the AVX instruction extensions.
30 - 29 Reserved Reserved
31 Not Used Always returns 0
More on Feature Information Returned in the EDX Register
Bit # Mnemonic Description
0 FPU Floating Point Unit On-Chip. The processor contains an x87 FPU.
1 VME Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
2 DE Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.
3 PSE Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.
4 TSC Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
5 MSR Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.
6 PAE Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1.
7 MCE Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
8 CX8 CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly locked and atomic).
9 APIC APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated).
10 Reserved Reserved
11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.
12 MTRR Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported.
13 PGE Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
14 MCA Machine Check Architecture. The Machine Check Architecture, which provides a compatible mechanism for error reporting in P6 family, Pentium 4, Intel Xeon processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.
15 CMOV Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
16 PAT Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity.
17 PSE-36 36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
18 PSN Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled.
19 CLFSH CLFLUSH Instruction. CLFLUSH Instruction is supported.
20 Reserved Reserved
21 DS Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see Chapter 20, "Introduction to Virtual-Machine Extensions," in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B).
22 ACPI Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.
23 MMX Intel MMX Technology. The processor supports the Intel MMX technology.
24 FXSR FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
25 SSE SSE. The processor supports the SSE extensions.
26 SSE2 SSE2. The processor supports the SSE2 extensions.
27 SS Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.
28 HTT Multi-Threading. The physical processor package is capable of supporting more than one logical processor.
29 TM Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).
30 Reserved Reserved
31 PBE Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.

INPUT EAX = 2: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX

When CPUID executes with EAX set to 2, the processor returns information about the processor's internal TLBs, cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form and fall into the following categories:

Encoding of CPUID Leaf 2 Descriptors
Value Type Description
00H General Null descriptor, this byte contains no information
01H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
02H TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries
03H TLB Data TLB: 4 KByte pages, 4-way set associative, 64 entries
04H TLB Data TLB: 4 MByte pages, 4-way set associative, 8 entries
05H TLB Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
06H Cache 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
08H Cache 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
09H Cache 1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
0AH Cache 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0BH TLB Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0CH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0DH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
0EH Cache 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
21H Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
22H Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
23H Cache 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
25H Cache 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
29H Cache 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
2CH Cache 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
30H Cache 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
40H Cache No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rdlevel cache
41H Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
42H Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
43H Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
44H Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
45H Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
46H Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
47H Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
48H Cache 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
49H Cache 3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
4AH Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
4BH Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
4CH Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
4DH Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
4EH Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
4FH TLB Instruction TLB: 4 KByte pages, 32 entries
50H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
51H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
52H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
55H TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
56H TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
57H TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries
59H TLB Data TLB0: 4 KByte pages, fully associative, 16 entries
5AH TLB Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries
5BH TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries
5CH TLB Data TLB: 4 KByte and 4 MByte pages,128 entries
5DH TLB Data TLB: 4 KByte and 4 MByte pages,256 entries
60H Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
66H Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
67H Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
68H Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
70H Cache Trace cache: 12 K-op, 8-way set associative
71H Cache Trace cache: 16 K-op, 8-way set associative
72H Cache Trace cache: 32 K-op, 8-way set associative
78H Cache 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
79H Cache 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7AH Cache 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7BH Cache 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7CH Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
7DH Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
7FH Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
80H Cache 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
82H Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
83H Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
84H Cache 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
85H Cache 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
86H Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
87H Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
B0H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
B1H TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
B2H TLB Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
B3H TLB Data TLB: 4 KByte pages, 4-way set associative, 128 entries
B4H TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries
BAH TLB Data TLB1: 4 KByte pages, 4-way associative, 64 entries
C0H TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
CAH STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
E4H Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
EAH Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
EBH Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
ECH Cache 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
F0H Prefetch 64-Byte prefetching
F1H Prefetch 128-Byte prefetching
FFH General CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters

Example of Cache and TLB Interpretation

The first member of the family of Pentium 4 processors returns the following information about caches and TLBs when the CPUID executes with an input value of 2:

EAX 66 5B 50 01H
EBX 0H
ECX 0H
EDX 00 7A 70 00H

Which means:

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level

When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0.

Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally defined fields reported by deterministic cache parameters are documented in "Information Returned by CPUID Instruction".

This Cache Size in Bytes = (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1) = (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (EXC + 1)

The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical package. This information is constant for all valid index values. Software can query the raw data reported by executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in Chapter 8, "Multiple-Processor Management," in theIntel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

INPUT EAX = 05H: Returns MONITOR and MWAIT Features

When CPUID executes with EAX set to 05H, the processor returns information about features available to MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management. See "Information Returned by CPUID Instruction".

INPUT EAX = 06H: Returns Thermal and Power Management Features

When CPUID executes with EAX set to 06H, the processor returns information about thermal and power management features. See "Information Returned by CPUID Instruction".

INPUT EAX = 09H: Returns Direct Cache Access Information

When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabilities. See "Information Returned by CPUID Instruction".

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features

When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see "Information Returned by CPUID Instruction") is greater thanPn 0. See "Information Returned by CPUID Instruction".

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover the programming facilities and the architectural performance events available in the processor. The details are described in Chapter20, "Introduction to Virtual-Machine Extensions," in theIntel®64 and IA-32 Architectures Software Developer's Manual, Volume 3B.

INPUT EAX = 0BH: Returns Extended Topology Information

When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumeration data. Software must detect the presence of CPUID leaf 0BH by verifying

See "Information Returned by CPUID Instruction".

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information

When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector representation of all processor state extensions that are supported in the processor and storage size requirements of the XSAVE/XRSTOR area. See "Information Returned by CPUID Instruction".

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area. See "Information Returned by CPUID Instruction".Software can use the forward-extendable technique depicted below to query the valid sub-leaves and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved
IF (CPUID.(EAX=0DH, ECX=0): VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX
Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;
FI;

METHODS FOR RETURNING BRANDING INFORMATION

Use the following techniques to access branding information:

These two methods are discussed in the following sections. For methods that are available in early processors, see Section: "Identification of Earlier IA-32 Processors" in Chapter 14 of the Intel®64 and IA-32 Architectures Software Developer's Manual,Volume 1.

The Processor Brand String Method

Figure 3-8 describes the algorithm used for detection of the brand string. Processorbrand identification software should execute this algorithm on all Intel 64 and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the maximum operating frequency of the processor to the EAX, EBX, ECX, and EDX registers.

How Brand Strings Work

To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-terminated.

The following table shows the brand string that is returned by the first processor in thePentium 4 processor family.

Processor Brand String Returned with Pentium 4 Processor
EAX Input Value Return Values ASCII Equivalent
80000002H EAX = 20202020H "    "
EBX = 20202020H "    "
ECX = 20202020H "    "
EDX = 6E492020H "nI  "
80000003H EAX = 286C6574H "(let"
EBX = 50202952H "P )R"
ECX = 69746E65H "itne"
EDX = 52286D75H "R(mu"
80000004H EAX = 20342029H " 4 )"
EBX = 20555043H " UPC"
ECX = 30303531H "0051"
EDX = 007A484DH "\0zHM"

Extracting the Maximum Processor Frequency from Brand Strings

Figure 3-9 provides an algorithm which software can use to extract the maximumprocessor operating frequency from the processor brand string.

Note: When a frequency is given in a brand string, it is the maximum qualified frequency of the processor, not the frequency at which the processor is currently running.

The Processor Brand Index Method

The brand index method (introduced with Pentium® III Xeon® processors) provides an entry point into a brand identification table that is maintained in memory by system software and is accessible from system- and user-level code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can then use this index to locate the brand identification string for the processor in the brand identification table. The first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead.

The following shows brand indices that have identification strings associated with them.

Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings
Brand Index Brand String
00H This processor does not support the brand identification feature
01H Intel(R) Celeron(R) processor1
02H Intel(R) Pentium(R) III processor1
03H Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R) processor
04H Intel(R) Pentium(R) III processor
06H Mobile Intel(R) Pentium(R) III processor-M
07H Mobile Intel(R) Celeron(R) processor1
08H Intel(R) Pentium(R) 4 processor
09H Intel(R) Pentium(R) 4 processor
0AH Intel(R) Celeron(R) processor1
0BH Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP
0CH Intel(R) Xeon(R) processor MP
0EH Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor
0FH Mobile Intel(R) Celeron(R) processor1
11H Mobile Genuine Intel(R) processor
12H Intel(R) Celeron(R) M processor
13H Mobile Intel(R) Celeron(R) processor1
14H Intel(R) Celeron(R) processor
15H Mobile Genuine Intel(R) processor
16H Intel(R) Pentium(R) M processor
17H Mobile Intel(R) Celeron(R) processor1
18H - 0FFH RESERVED

Notes: 1. Indicates versions of these processors that were introduced after the Pentium III

Pseudo Code

IA32_BIOS_SIGN_ID MSR = Update with installed microcode revision number;
CASE (EAX) OF
	EAX = 0:
		EAX = Highest basic function input value understood by CPUID;
		EBX = Vendor identification string;
		EDX = Vendor identification string;
		ECX = Vendor identification string;
		BREAK;
	EAX = 1H:
		EAX[3:0] = Stepping ID;
		EAX[7:4] = Model;
		EAX[11:8] = Family;
		EAX[13:12] = Processor type;
		EAX[15:14] = Reserved;
		EAX[19:16] = Extended Model;
		EAX[27:20] = Extended Family;
		EAX[31:28] = Reserved;
		EBX[7:0] = Brand Index; (* Reserved if the value is zero. *)
		EBX[15:8] = CLFLUSH Line Size;
		EBX[16:23] = Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
		EBX[24:31] = Initial APIC ID;
		ECX = Feature flags; (* See Figure 3-6. *)
		EDX = Feature flags; (* SeeFigure 3-7. *)
		BREAK;
	EAX = 2H:
		EAX = Cache and TLB information;
		EBX = Cache and TLB information;
		ECX = Cache and TLB information;
		EDX = Cache and TLB information;
		BREAK;
	EAX = 3H:
		EAX = Reserved;
		EBX = Reserved;
		ECX = ProcessorSerialNumber[31:0];
		(* Pentium III processors only, otherwise reserved. *)
		EDX = ProcessorSerialNumber[63:32];
		(* Pentium III processors only, otherwise reserved. *)
		BREAK;
	EAX = 4H:
		EAX = Deterministic Cache Parameters Leaf; (* SeeTable 3-12. *)
		EBX = Deterministic Cache Parameters Leaf;
		ECX = Deterministic Cache Parameters Leaf;
		EDX = Deterministic Cache Parameters Leaf;
		BREAK;
	EAX = 5H:
		EAX = MONITOR/MWAIT Leaf; (* SeeTable 3-12. *)
		EBX = MONITOR/MWAIT Leaf;
		ECX = MONITOR/MWAIT Leaf;
		EDX = MONITOR/MWAIT Leaf;
		BREAK;
	EAX = 6H:
		EAX = Thermal and Power Management Leaf; (* SeeTable 3-12. *)
		EBX = Thermal and Power Management Leaf;
		ECX = Thermal and Power Management Leaf;
		EDX = Thermal and Power Management Leaf;
		BREAK;
	EAX = 7H or 8H:
		EAX = Reserved = 0;
		EBX = Reserved = 0;
		ECX = Reserved = 0;
		EDX = Reserved = 0;
		BREAK;
	EAX = 9H:
		EAX = Direct Cache Access Information Leaf; (* SeeTable 3-12. *)
		EBX = Direct Cache Access Information Leaf;
		ECX = Direct Cache Access Information Leaf;
		EDX = Direct Cache Access Information Leaf;
		BREAK;
	EAX = AH:
		EAX = Architectural Performance Monitoring Leaf; (* SeeTable 3-12. *)
		EBX = Architectural Performance Monitoring Leaf;
		ECX = Architectural Performance Monitoring Leaf;
		EDX = Architectural Performance Monitoring Leaf;
		BREAK
	EAX = BH:
		EAX = Extended Topology Enumeration Leaf; (* SeeTable 3-12. *)
		EBX = Extended Topology Enumeration Leaf;
		ECX = Extended Topology Enumeration Leaf;
		EDX = Extended Topology Enumeration Leaf;
		BREAK;
	EAX = CH:
		EAX = Reserved = 0;
		EBX = Reserved = 0;
		ECX = Reserved = 0;
		EDX = Reserved = 0;
		BREAK;
	EAX = DH:
		EAX = Processor Extended State Enumeration Leaf; (* SeeTable 3-12. *)
		EBX = Processor Extended State Enumeration Leaf;
		ECX = Processor Extended State Enumeration Leaf;
		EDX = Processor Extended State Enumeration Leaf;
		BREAK;
	EAX = 80000000H:
		EAX = Highest extended function input value understood by CPUID;
		EBX = Reserved;
		ECX = Reserved;
		EDX = Reserved;
		BREAK;
	EAX = 80000001H:
		EAX = Reserved;
		EBX = Reserved;
		ECX = Extended Feature Bits (* See Table 3-12. *);
		EDX = Extended Feature Bits (* See Table 3-12. *);
		BREAK;
	EAX = 80000002H:
		EAX = Processor Brand String;
		EBX = Processor Brand String, continued;
		ECX = Processor Brand String, continued;
		EDX = Processor Brand String, continued;
		BREAK;
	EAX = 80000003H:
		EAX = Processor Brand String, continued;
		EBX = Processor Brand String, continued;
		ECX = Processor Brand String, continued;
		EDX = Processor Brand String, continued;
		BREAK;
	EAX = 80000004H:
		EAX = Processor Brand String, continued;
		EBX = Processor Brand String, continued;
		ECX = Processor Brand String, continued;
		EDX = Processor Brand String, continued;
		BREAK;
	EAX = 80000005H:
		EAX = Reserved = 0;
		EBX = Reserved = 0;
		ECX = Reserved = 0;
		EDX = Reserved = 0;
		BREAK;
	EAX = 80000006H:
		EAX = Reserved = 0;
		EBX = Reserved = 0;
		ECX = Cache information;
		EDX = Reserved = 0;
		BREAK;
	EAX = 80000007H:
		EAX = Reserved = 0;
		EBX = Reserved = 0;
		ECX = Reserved = 0;
		EDX = Reserved = Misc Feature Flags;
		BREAK;
	EAX = 80000008H:
		EAX = Reserved = Physical Address Size Information;
		EBX = Reserved = Virtual Address Size Information;
		ECX = Reserved = 0;
		EDX = Reserved = 0;
		BREAK;
	EAX >= 40000000H and EAX <= 4FFFFFFFH:
		DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
		(* If the highest basic information leaf data depend on ECX input value, ECX is honored. *)
		EAX = Reserved; (* Information returned for highest basic information leaf. *)
		EBX = Reserved; (* Information returned for highest basic information leaf. *)
		ECX = Reserved; (* Information returned for highest basic information leaf. *)
		EDX = Reserved; (* Information returned for highest basic information leaf. *)
		BREAK;
ESAC;

Flags Affected

None.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used. In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.

Compatibility Mode Exceptions

Exception Description
#UD If the LOCK prefix is used. In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used. In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used. In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used. In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.