EXTRACTPS

Extract Packed Single Precision Floating-Point Value

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 3A 17 /r ib EXTRACTPS reg/m32, xmm2, imm8 A Valid Valid Extract a single-precision floating-point value from xmm2 at the source offset specified by imm8 and store the result to reg or m32. The upper 32 bits of r64 is zeroed if reg is r64.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:reg (r) ModRM:r/m (w)

Description

Extract a single-precision floating-point value from the source xmm register (second argument) at an offset determined by imm8[1-0]*32. The extracted single precision floating-point value is stored into the low 32-bits of the destination register or to the 32-bit memory location.

When in 64-bit mode and the destination operand is a general purpose register (GPR), the default operand size is 64 bits. The upper 32 bits of the 64-bit register is filled with zero.

Pseudo Code

IF (64-Bit Mode and the destination is a GPR)
	DEST[31:0] = (SRC >> (32 * imm8[1:0])) AND 0FFFFFFFFh;
	DEST[63:32] = ZERO_FILL;
ELSE
	DEST[31:0] = (SRC >> (32 * imm8[1:0])) AND 0FFFFFFFFh;
FI;

Exceptions

SIMD Floating-Point Exceptions

None

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP if any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.