FADD/FADDP/FIADD

Add

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DE /0 FIADD m16int None Valid Valid Add m16int to ST(0) and store result in ST(0).
DA /0 FIADD m32int None Valid Valid Add m32int to ST(0) and store result in ST(0).
DE C1 FADDP None Valid Valid Add ST(0) to ST(1), store result in ST(1), and pop the register stack.
DE C0+i FADDP ST(i), ST(0) None Valid Valid Add ST(0) to ST(i), store result in ST(i), and pop the register stack.
DC C0+i FADD ST(i), ST(0) None Valid Valid Add ST(i) to ST(0) and store result in ST(i).
D8 C0+i FADD ST(0), ST(i) None Valid Valid Add ST(0) to ST(i) and store result in ST(0).
DC /0 FADD m64fp None Valid Valid Add m64fp to ST(0) and store result in ST(0).
D8 /0 FADD m32fp None Valid Valid Add m32fp to ST(0) and store result in ST(0).

Description

Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.

The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-operand version adds the contents of a memory location (either a floating-point or an integer value) to the contents of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice versa. The value in ST(0) can be doubled by coding:

FADD ST(0), ST(0);

The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. (The no-operand version of the floating-point add instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)

The FIADD instructions convert an integer source operand to double extended-precision floating-point format before performing the addition.

The table on the following page shows the results obtained when adding various classes of numbers, assuming that neither overflow nor underflow occurs.

When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward -∞ mode, in which case the result is -0. When the source operand is an integer 0, it is treated as a +0.

When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infinities of opposite signs, an invalid-operation exception is generated. See the following table.

FADD/FADDP/FIADD Results
DEST
SRC
- ∞ - F - 0 + 0 + F + ∞ NaN
- ∞ - ∞ - ∞ - ∞ - ∞ - ∞ * NaN
-F or -I - ∞ - F SRC SRC ± F or ± 0 + ∞ NaN
- 0 - ∞ DEST - 0 ± 0 DEST + ∞ NaN
+ 0 - ∞ DEST ± 0 + 0 DEST + ∞ NaN
+ F or + I - ∞ ± F or ± 0 SRC SRC + F + ∞ NaN
+ ∞ * + ∞ + ∞ + ∞ + ∞ + ∞ NaN
NaN NaN NaN NaN NaN NaN NaN NaN

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF Instruction = FIADD
	DEST = DEST + ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE
	(* Source operand is floating-point value *)
	DEST = DEST + SRC;
FI;
IF Instruction = FADDP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#O Result is too large for destination format.
#U Result is too small for destination format.
#D Source operand is a denormal value.
#IA Operand is an SNaN value or unsupported format. Operands are infinities of unlike sign.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.