FCOMI/FCOMIP/FUCOMI/FUCOMIP

Compare Floating Point Values and Set EFLAGS

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DF E8+i FUCOMIP ST, ST(i) None Valid Valid Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack.
DB E8+i FUCOMI ST, ST(i) None Valid Valid Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly.
DF F0+i FCOMIP ST, ST(i) None Valid Valid Compare ST(0) with ST(i), set status flags accordingly, and pop register stack.
DB F0+i FCOMI ST, ST(i) None Valid Valid Compare ST(0) with ST(i) and set status flags accordingly.

Description

Performs an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and CF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for comparisons, so that -0.0 is equal to +0.0.

FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results
Comparison Results* ZF PF CF
ST(0) > ST(i) 0 0 0
ST(0) < ST(i) 0 0 1
ST(0) = ST(i) 1 0 0
Unordered** 1 1 1

An unordered comparison checks the class of the numbers being compared (see "FXAM—Examine ModR/M" in this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instructions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions raise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an unsupported format.

If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS register are set only if the exception is masked.

The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions clear the OF flag in the EFLAGS register (regardless of whether an invalid-operation exception is detected).

The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

CASE (relation of operands) OF
	ST(0) > ST(i): ZF, PF, CF = 000;
	ST(0) < ST(i): ZF, PF, CF = 001;
	ST(0) = ST(i): ZF, PF, CF = 100;
ESAC;
IF Instruction is FCOMI or FCOMIP
	IF ST(0) or ST(i) = NaN or unsupported format
		#IA
		IF FPUControlWord.IM = 1
			ZF, PF, CF = 111;
		FI;
	FI;
FI;
IF Instruction is FUCOMI or FUCOMIP
	IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format
		ZF, PF, CF = 111;
	ELSE
		(* ST(0) or ST(i) is SNaN or unsupported format *)
		#IA;
		IF FPUControlWord.IM = 1
			ZF, PF, CF = 111;
		FI;
	FI;
FI;
IF Instruction is FCOMIP or FUCOMIP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 Not affected.

Exceptions

Floating-Point Exceptions

Exception Description
#IA (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported formats. (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or have undefined formats. Detection of a QNaN value does not raise an invalid-operand exception.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.