FDIV/FDIVP/FIDIV

Divide

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DE /6 FIDIV m16int None Valid Valid Divide ST(0) by m64int and store result in ST(0).
DA /6 FIDIV m32int None Valid Valid Divide ST(0) by m32int and store result in ST(0).
DE F9 FDIVP None Valid Valid Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
DE F8+i FDIVP ST(i), ST(0) None Valid Valid Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
DC F8+i FDIV ST(i), ST(0) None Valid Valid Divide ST(i) by ST(0) and store result in ST(i).
D8 F0+i FDIV ST(0), ST(i) None Valid Valid Divide ST(0) by ST(i) and store result in ST(0).
DC /6 FDIV m64fp None Valid Valid Divide ST(0) by m64fp and store result in ST(0).
D8 /6 FDIV m32fp None Valid Valid Divide ST(0) by m32fp and store result in ST(0).

Description

Divides the destination operand by the source operand and stores the result in the destination location. The destination operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.

The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0) register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location (either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by the contents of the ST(i) register or vice versa.

The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.

The FIDIV instructions convert an integer source operand to double extended-precision floating-point format before performing the division. When the source operand is an integer 0, it is treated as a +0.

If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand.

The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs.

FDIV/FDIVP/FIDIV Results
DEST
SRC
- infin - F - 0 + 0 + F + infin NaN
- infin * + 0 + 0 - 0 - 0 * NaN
- F + infin + F + 0 - 0 - F - infin NaN
- I + infin + F + 0 - 0 - F - infin NaN
- 0 + infin ** * * ** - infin NaN
+ 0 - infin ** * * ** + infin NaN
+ I - infin - F - 0 + 0 + F + infin NaN
+ F - infin - F - 0 + 0 + F + infin NaN
+ infin * - 0 - 0 + 0 + 0 * NaN
NaN NaN NaN NaN NaN NaN NaN NaN

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF SRC = 0
	#Z;
ELSE
	IF Instruction is FIDIV
		DEST = DEST / ConvertToDoubleExtendedPrecisionFP(SRC);
	ELSE
		(* Source operand is floating-point value *)
		DEST = DEST / SRC;
	FI;
FI;
IF Instruction = FDIVP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#O Result is too large for destination format.
#U Result is too small for destination format.
#Z DEST / 0, where DEST is not equal to 0.
#IA Operand is an SNaN value or unsupported format. ∞ / ∞; 0 / 0 #D Source is a denormal value.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.