FDIVR/FDIVRP/FIDIVR

Reverse Divide

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DE /7 FIDIVR m16int None Valid Valid Divide m16int by ST(0) and store result in ST(0).
DA /7 FIDIVR m32int None Valid Valid Divide m32int by ST(0) and store result in ST(0).
DE F1 FDIVRP None Valid Valid Divide ST(0) by ST(1), store result in ST(1), and pop the register stack.
DE F0+i FDIVRP ST(i), ST(0) None Valid Valid Divide ST(0) by ST(i), store result in ST(i), and pop the register stack.
DC F0+i FDIVR ST(i), ST(0) None Valid Valid Divide ST(0) by ST(i) and store result in ST(i).
D8 F8+i FDIVR ST(0), ST(i) None Valid Valid Divide ST(i) by ST(0) and store result in ST(0).
DC /7 FDIVR m64fp None Valid Valid Divide m64fp by ST(0) and store result in ST(0).
D8 /7 FDIVR m32fp None Valid Valid Divide m32fp by ST(0) and store result in ST(0).

Description

Divides the source operand by the destination operand and stores the result in the destination location. The destination operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.

These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to support more efficient coding.

The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1) register. The one-operand version divides the contents of a memory location (either a floating-point or an integer value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by the contents of the ST(0) register or vice versa.

The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.

The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format before performing the division.

If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand.

The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs.

FDIV/FDIVP/FIDIV Results
DEST
SRC
- ∞ - F - 0 + 0 + F + ∞ NaN
- ∞ * + ∞ + ∞ - ∞ - ∞ * NaN
- F + 0 + F ** ** - F - 0 NaN
- I + 0 + F ** ** - F - 0 NaN
- 0 + 0 + 0 * * - 0 - 0 NaN
+ 0 - 0 - 0 * * + 0 + 0 NaN
+ I - 0 - F ** ** + F + 0 NaN
+ F - 0 - F ** ** + F + 0 NaN
+ ∞ * - ∞ - ∞ + ∞ + ∞ * NaN
NaN NaN NaN NaN NaN NaN NaN NaN

When the source operand is an integer 0, it is treated as a +0. This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF DEST = 0
	#Z;
ELSE
	IF Instruction = FIDIVR
		DEST = ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;
	ELSE
		(* Source operand is floating-point value *)
		DEST = SRC / DEST;
	FI;
FI;
IF Instruction = FDIVRP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#O Result is too large for destination format.
#U Result is too small for destination format.
#Z SRC / 0, where SRC is not equal to 0.
#IA Operand is an SNaN value or unsupported format. ∞ / ∞; 0 / 0 #D Source is a denormal value.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.