FIST/FISTP

Store Integer

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DF /7 FISTP m64int None Valid Valid Store ST(0) in m64int and pop register stack.
DB /3 FISTP m32int None Valid Valid Store ST(0) in m32int and pop register stack.
DF /3 FISTP m16int None Valid Valid Store ST(0) in m16int and pop register stack.
DB /2 FIST m32int None Valid Valid Store ST(0) in m32int.
DF /2 FIST m16int None Valid Valid Store ST(0) in m16int.

Description

The FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the destination operand. Values can be stored in word or double-word integer format. The destination operand specifies the address where the first byte of the destination value is to be stored.

The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FISTP instruction also stores values in quadword integer format.

The following table shows the results obtained when storing various classes of numbers in integer format.

FIST/FISTP Results
ST(0) DEST
- ∞ or Value Too Large for DEST Format *
F ≤ -1 - I
-1 < F < -0 **
- 0 0
+ 0 0
+ 0 < F < + 1 **
F ≥ + 1 + I
+ ∞ or Value Too Large for DEST Format *
NaN *

If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode specified by the RC field of the FPU control word.

If the converted value is too large for the destination format, or if the source operand is an ∞, SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is not masked, an invalidarithmetic-operand exception (#IA) is generated and no value is stored in the destination operand. If the invalid-operation exception is masked, the integer indefinite value is stored in memory.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

DEST = Integer(ST(0));
IF Instruction = FISTP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Indicates rounding direction of if the inexact exception (#P) is generated: 0 = not roundup; 1 = roundup. Set to 0 otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#IA Converted value is too large for the destination format. Source operand is an SNaN, QNaN, ∞, or unsupported format.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.