FMUL/FMULP/FIMUL

Multiply

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DE /1 FIMUL m16int None Valid Valid Multiply ST(0) by m16int and store result in ST(0).
DA /1 FIMUL m32int None Valid Valid Multiply ST(0) by m32int and store result in ST(0).
DE C9 FMULP None Valid Valid Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack.
DE C8+i FMULP ST(i), ST(0) None Valid Valid Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack.
DC C8+i FMUL ST(i), ST(0) None Valid Valid Multiply ST(i) by ST(0) and store result in ST(i).
D8 C8+i FMUL ST(0), ST(i) None Valid Valid Multiply ST(0) by ST(i) and store result in ST(0).
DC /1 FMUL m64fp None Valid Valid Multiply ST(0) by m64fp and store result in ST(0).
D8 /1 FMUL m32fp None Valid Valid Multiply ST(0) by m32fp and store result in ST(0).

Description

Multiplies the destination and source operands and stores the product in the destination location. The destination operand is always an FPU data register; the source operand can be an FPU data register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.

The no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0) register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) register by the contents of a memory location (either a floating point or an integer value) and stores the product in the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the destination operand).

The FMULP instructions perform the additional operation of popping the FPU register stack after storing the product. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.

The FIMUL instructions convert an integer source operand to double extended-precision floating-point format before performing the multiplication.

The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multiplied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0.

The following table shows the results obtained when multiplying various classes of numbers, assuming that neither overflow nor underflow occurs.

FMUL/FMULP/FIMUL Results
DEST
SRC
-∞ -F -0 +0 +F +∞ NaN
-∞ +∞ +∞ * * -∞ -∞ NaN
-F +∞ +F +0 -0 -F -∞ NaN
-I +∞ +F +0 -0 -F -∞ NaN
-0 * +0 +0 -0 -0 * NaN
+0 * -0 -0 +0 +0 * NaN
+I -∞ -F -0 +0 +F +∞ NaN
+F -∞ -F -0 +0 +F +∞ NaN
+∞ -∞ -∞ * * +∞ +∞ NaN
NaN NaN NaN NaN NaN NaN NaN NaN

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF Instruction = FIMUL
	DEST = DEST * ConvertToDoubleExtendedPrecisionFP(SRC);
ELSE
	(* Source operand is floating-point value *)
	DEST = DEST * SRC;
FI;
IF Instruction = FMULP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#O Result is too large for destination format.
#U Result is too small for destination format.
#D Source operand is a denormal value.
#IA Operand is an SNaN value or unsupported format. One operand is 0 and the other is ∞.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.