FSUBR/FSUBRP/FISUBR

Reverse Subtract

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
DE /5 FISUBR m16int None Valid Valid Subtract ST(0) from m16int and store result in ST(0).
DA /5 FISUBR m32int None Valid Valid Subtract ST(0) from m32int and store result in ST(0).
DE E1 FSUBRP None Valid Valid Subtract ST(1) from ST(0), store result in ST(1), and pop register stack.
DE E0+i FSUBRP ST(i), ST(0) None Valid Valid Subtract ST(i) from ST(0), store result in ST(i), and pop register stack.
DC E0+i FSUBR ST(i), ST(0) None Valid Valid Subtract ST(i) from ST(0)and store result in ST(i).
D8 E8+i FSUBR ST(0), ST(i) None Valid Valid Subtract ST(0) from ST(i) and store result in ST(0).
DC /5 FSUBR m64fp None Valid Valid Subtract ST(0) from m64fp and store result in ST(0).
D8 /5 FSUBR m32fp None Valid Valid Subtract ST(0) from m32fp and store result in ST(0).

Description

Subtracts the destination operand from the source operand and stores the difference in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.

These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions. They are provided to support more efficient coding.

The no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and stores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents of a memory location (either a floating-point or an integer value) and stores the result in ST(0). The two-operand version, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.

The FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.

The FISUBR instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.

The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the DEST value is subtracted from the SRC value (SRC - DEST = result).

When the difference between two operands of like sign is 0, the result is +0, except for the round toward -∞ mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) =+0, and that -0 - (+0) =-0. When the source operand is an integer 0, it is treated as a +0.

When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ of the same sign, an invalid-operation exception is generated.

FSUBR/FSUBRP/FISUBR Results
DEST
SRC
-∞ -F or-I -0 +0 +F or +I +∞ NaN
-∞ * +∞ +∞ +∞ +∞ +∞ NaN
-F -∞ ±F or ±0 -DEST -DEST +F +∞ NaN
-0 -∞ SRC ±0 +0 SRC +∞ NaN
+0 -∞ SRC -0 ±0 SRC +∞ NaN
+F -∞ -F -DEST -DEST ±F or ±0 +∞ NaN
+∞ -∞ -∞ -∞ -∞ -∞ * NaN
NaN NaN NaN NaN NaN NaN NaN NaN

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF Instruction = FISUBR
	DEST = ConvertToDoubleExtendedPrecisionFP(SRC) - DEST;
ELSE
	(* Source operand is floating-point value *)
	DEST = SRC - DEST;
FI;
IF Instruction = FSUBRP
	PopRegisterStack;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#P Value cannot be represented exactly in destination format.
#O Result is too large for destination format.
#U Result is too small for destination format.
#D Source operand is a denormal value.
#IA Operand is an SNaN value or unsupported format. Operands are infinities of like sign.
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.