FXCH

Exchange Register Contents

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
D9 C9 FXCH None Valid Valid Exchange the contents of ST(0) and ST(1).
D9 C8+i FXCH ST(i) None Valid Valid Exchange the contents of ST(0) and ST(i).

Description

Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.

This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack:

FXCH ST(3);
FSQRT;
FXCH ST(3);

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Pseudo Code

IF (Number-of-operands) is 1
	temp = ST(0);
	ST(0) = SRC;
	SRC = temp;
ELSE
	temp = ST(0);
	ST(0) = ST(1);
	ST(1) = temp;
FI;

FPU Flags Affected

C1: Set to 0 if stack underflow occurred; otherwise, set to 1. C0, C2, C3 are undefined.

Exceptions

Floating-Point Exceptions

Exception Description
#IS Stack underflow occurred.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#MF If there is a pending x87 FPU exception.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.