IMUL

Signed Multiply

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX.W + 69 /r id IMUL r64, r/m64, C Valid N.E. Quadword register = r/m64 imm32 * immediate doubleword.
69 /r id IMUL r32, r/m32, C Valid Valid doubleword register = imm32 r/m32 * immediate doubleword.
69 /r iw IMUL r16, r/m16, C Valid Valid word register = r/m16 * imm16 immediate word.
REX.W + 6B /r ib IMUL r64, r/m64, C Valid N.E. Quadword register = r/m64 imm8 * sign-extended immediate byte.
6B /r ib IMUL r32, r/m32, C Valid Valid doubleword register = imm8 r/m32 * sign-extended immediate byte.
6B /r ib IMUL r16, r/m16, C Valid Valid word register = r/m16 * imm8 sign-extended immediate byte.
REX.W + 0F AF IMUL r64, r/m64 B Valid N.E. Quadword register = /r Quadword register * r/m64.
0F AF /r IMUL r32, r/m32 B Valid Valid doubleword register = doubleword register * r/m32.
0F AF /r IMUL r16, r/m16 B Valid Valid word register = word register * r/m16.
REX.W + F7 /5 IMUL r/m64 A Valid N.E. RDX:RAX = RAX * r/m64.
F7 /5 IMUL r/m32 A Valid Valid EDX:EAX = EAX * r/m32.
F7 /5 IMUL r/m16 A Valid Valid DX:AX = AX * r/m word.
F6 /5 IMUL r/m8* A Valid Valid AX= AL * r/m byte.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
C NA imm8/16/32 ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The CF and OF flags are set when significant bit (including the sign bit) are carried into the upper half of the result. The CF and OF flags are cleared when the result (including the sign bit) fits exactly in the lower half of the result.

The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, the result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.

The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three forms of the instruction as follows.

Pseudo Code

IF (NumberOfOperands = 1)
	IF (OperandSize = 8)
		AX = AL * SRC (* Signed multiplication *)
		IF AL = AX
			CF = 0;
			OF = 0;
		ELSE
			CF = 1;
			OF = 1;
		FI;
	ELSE
		IF OperandSize = 16
			DX:AX = AX * SRC (* Signed multiplication *)
			IF sign_extend_to_32 (AX) = DX:AX
				CF = 0;
				OF = 0;
			ELSE
				CF = 1;
				OF = 1;
			FI;
		ELSE
			IF OperandSize = 32
				EDX:EAX = EAX * SRC (* Signed multiplication *)
				IF EAX = EDX:EAX
					CF = 0;
					OF = 0;
				ELSE
					CF = 1;
					OF = 1;
				FI;
			ELSE
				(* OperandSize = 64 *)
				RDX:RAX = RAX * SRC (* Signed multiplication *)
				IF RAX = RDX:RAX
					CF = 0;
					OF = 0;
				ELSE
					CF = 1;
					OF = 1;
				FI;
			FI;
		FI;
	FI;
ELSE
	IF (NumberOfOperands = 2)
		temp = DEST * SRC (* Signed multiplication; temp is double DEST size *)
		DEST = DEST * SRC (* Signed multiplication *)
		IF temp != DEST
			CF = 1;
			OF = 1;
		ELSE
			CF = 0;
			OF = 0;
		FI;
	ELSE
		(* NumberOfOperands = 3 *)
		DEST = SRC1 * SRC2 (* Signed multiplication *)
		temp = SRC1 * SRC2 (* Signed multiplication; temp is double SRC1 size *)
		IF temp != DEST
			CF = 1;
			OF = 1;
		ELSE
			CF = 0;
			OF = 0;
		FI;
	FI;
FI;

Flags Affected

For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL segment selector.