INSERTPS

Insert Packed Single Precision Floating-Point Value

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 3A 21 /r ib INSERTPS xmm1, xmm2/m32, imm8 A Valid Valid Insert a single precision floating-point value selected by imm8 from xmm2/m32 into xmm1 at the specified destination element specified by imm8 and zero out destination elements in xmm1 as indicated in imm8.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:r/m (r) ModRM:reg (w)

Description

Insert a single-precision floating-point value from the source operand (second operand) into a specified location in the destination register operand (first operand) and selectively zero out the data elements in the destination according to the mask field in the immediate byte (third operand). The source operand can be a memory location (32 bits) or an XMM register.

The immediate byte provides three fields:

COUNT_S: The value of Imm8[7:6] selects the dword element from the source register; it is 0 if the source is a memory operand.

COUNT_D: The value of Imm8[5:4] selects the target dword element in the destination register.

ZMASK: Each bit of Imm8[3:0] selects a dword element in the destination register to be written with 0.0 if set to 1.

Pseudo Code

IF (SRC = REG)
	COUNT_S = imm8[7:6];
ELSE
	COUNT_S = 0;
FI;
COUNT_D = imm8[5:4];
ZMASK = imm8[3:0];
CASE (COUNT_S) OF
	0: TMP = SRC[31:0];
	1: TMP = SRC[63:32];
	2: TMP = SRC[95:64];
	3: TMP = SRC[127:96];
ESAC;
CASE (COUNT_D) OF
	0: TMP2[31:0] = TMP;
	TMP2[127:32] = DEST[127:32];
	1: TMP2[63:32] = TMP;
	TMP2[31:0] = DEST[31:0];
	TMP2[127:64] = DEST[127:64];
	2: TMP2[95:64] = TMP;
	TMP2[63:0] = DEST[63:0];
	TMP2[127:96] = DEST[127:96];
	3: TMP2[127:96] = TMP;
	TMP2[95:0] = DEST[95:0];
ESAC;
IF (ZMASK[0] = 1)
	DEST[31:0] = 00000000H;
ELSE
	DEST[31:0] = TMP2[31:0];
	IF (ZMASK[1] = 1)
		DEST[63:32] = 00000000H;
	ELSE
		DEST[63:32] = TMP2[63:32];
		IF (ZMASK[2] = 1)
			DEST[95:64] = 00000000H;
		ELSE
			DEST[95:64] = TMP2[95:64];
			IF (ZMASK[3] = 1)
				DEST[127:96] = 00000000H;
			ELSE
				DEST[127:96] = TMP2[127:96];
			FI;
		FI;
	FI;
FI;

Exceptions

SIMD Floating-Point Exceptions

None

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) if any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.