INVVPID

Invalidate Translations Based on VPID

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 38 81 INVVPID r32, m128 None None None Invalidates entries in the TLBs and paging-structure caches based on VPID (outside 64-bit mode)
66 0F 38 81 INVVPID r64, m128 None None None Invalidates entries in the TLBs and paging-structure caches based on VPID (in 64-bit mode)

Description

Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on virtual-processor identifier (VPID). (See Chapter 25,"Support for Address Translation" inIA-32 Intel Architecture Software Developer's Manual, Volume 3B.) Invalidation is based on the INVVPID type specified in the register operand and the INVVPID descriptor specified in the memory operand.

Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode, the register operand has 64 bits; however, if bits 63:32 of the register operand are not zero, INVVPID fails due to an attempt to use an unsupported INVVPID type (see below).

The INVVPID types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see Appendix "VMX Capability Reporting Facility" in IA-32 Intel Architecture Software Developer's Manual, Volume 3B). There are four INVVPID types currently defined:

If an unsupported INVVPID type is specified, the instruction fails.

INVVPID invalidates all the specified mappings for the indicated VPID(s) regardless of the EPTP and PCID values with which those mappings may be associated.

The INVVPID descriptor comprises 128 bits and consists of a VPID and a linear address.

Pseudo Code

IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
	#UD;
ELSE
	IF in VMX non-root operation
		VM exit;
	ELSE
		IF CPL > 0
			#GP(0);
		ELSE
			INVVPID_TYPE = value of register operand;
			IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support INVVPID_TYPE
				VMfail(Invalid operand to INVEPT/INVVPID);
			ELSE
				(* INVVPID_TYPE must be in the range 0-3 *)
				INVVPID_DESC = value of memory operand;
				IF INVVPID_DESC[63:16] != 0
					VMfail(Invalid operand to INVEPT/INVVPID);
				ELSE
					CASE INVVPID_TYPE OF
						0: (* individual-address invalidation VPID = INVVPID_DESC[15:0]; *)
							IF VPID = 0
								VMfail(Invalid operand to INVEPT/INVVPID);
							ELSE
								GL_ADDR = INVVPID_DESC[127:64];
								IF (GL_ADDR is not in a canonical form)
									VMfail(Invalid operand to INVEPT/INVVPID);
								ELSE
									Invalidate mappings for GL_ADDR tagged with VPID;
									VMsucceed;
								FI;
							FI;
							BREAK;
						1: (* single-context invalidation VPID_CTX = INVVPID_DESC[15:0]; *)
							IF VPID = 0
								VMfail(Invalid operand to INVEPT/INVVPID);
							ELSE
								Invalidate all mappings tagged with VPID;
								VMsucceed;
							FI;
							BREAK;
						2: (* all-context invalidation Invalidate all mappings tagged with all non-zero VPIDs; *)
							VMsucceed;
							BREAK;
						3: (* single-context invalidation retaining globals VPID = INVVPID_DESC[15:0]; *)
							IF VPID = 0
								VMfail(Invalid operand to INVEPT/INVVPID);
							ELSE
								Invalidate all mappings tagged with VPID except global translations;
								VMsucceed;
							FI;
							BREAK;
					ESAC;
				FI;
			FI;
		FI;
	FI;
FI;

Flags Affected

See the operation section and Section 5.2.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If not in VMX operation. If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0). If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).
#SS(0) If the memory destination operand is in the SS segment and the memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs in accessing the memory operand.
#GP(0) If the current privilege level is not 0. If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Exception Description
#UD The INVVPID instruction is not recognized in compatibility mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD The INVVPID instruction is not recognized in virtual-8086 mode.

Real-Address Mode Exceptions

Exception Description
#UD A logical processor cannot be in real-address mode while in VMX operation and the INVVPID instruction is not recognized outside VMX operation.

Protected Mode Exceptions

Exception Description
#UD If not in VMX operation. If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0). If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0).
#SS(0) If the memory operand effective address is outside the SS segment limit. If the SS register contains an unusable segment.
#PF(fault-code) If a page fault occurs in accessing the memory operand.
#GP(0) If the current privilege level is not 0. If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains an unusable segment. If the source operand is located in an execute-only code segment.