Jcc

Jump if Condition Is Met

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
7E cb JNG rel8 A Valid Valid Jump short if not greater (ZF=1 or SF OF).
75 cb JNE rel8 A Valid Valid Jump short if not equal (ZF=0).
73 cb JNC rel8 A Valid Valid Jump short if not carry (CF=0).
77 cb JNBE rel8 A Valid Valid Jump short if not below or equal (CF=0 and ZF=0).
73 cb JNB rel8 A Valid Valid Jump short if not below (CF=0).
72 cb JNAE rel8 A Valid Valid Jump short if not above or equal (CF=1).
76 cb JNA rel8 A Valid Valid Jump short if not above (CF=1 or ZF=1).
7E cb JLE rel8 A Valid Valid Jump short if less or equal (ZF=1 or SF OF).
7C cb JL rel8 A Valid Valid Jump short if less (SF OF).
7D cb JGE rel8 A Valid Valid Jump short if greater or equal (SF=OF).
7F cb JG rel8 A Valid Valid Jump short if greater (ZF=0 and SF=OF).
74 cb JE rel8 A Valid Valid Jump short if equal (ZF=1).
E3 cb JRCXZ rel8 A Valid N.E. Jump short if RCX register is 0.
E3 cb JECXZ rel8 A Valid Valid Jump short if ECX register is 0.
E3 cb JCXZ rel8 A N.E. Valid Jump short if CX register is 0.
72 cb JC rel8 A Valid Valid Jump short if carry (CF=1).
76 cb JBE rel8 A Valid Valid Jump short if below or equal (CF=1 or ZF=1).
72 cb JB rel8 A Valid Valid Jump short if below (CF=1).
73 cb JAE rel8 A Valid Valid Jump short if above or equal (CF=0).
77 cb JA rel8 A Valid Valid Jump short if above (CF=0 and ZF=0).

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA NA Offset

Description

Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code

(cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc instruction.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits.

The conditions for each Jcc mnemonic are given in the "Description" column of the table on the preceding page. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or equal) instruction are alternate mnemonics for the opcode 77H.

The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction, and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the following conditional far jump is illegal:

JZ FARLABEL;

To accomplish this far jump, use the following two instructions:

JNZ BEYOND;

JMP FARLABEL;

BEYOND:

The JRCXZ, JECXZ and JCXZ instructions differ from other Jcc instructions because they do not check status flags. Instead, they check RCX, ECX or CX for 0. The register checked is determined by the address-size attribute. These instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction (such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RCX, ECX or CX is 0. This would cause the loop to execute 264, 232 or 64K times (not zero times).

All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cacheability.

In 64-bit mode, operand size is fixed at 64 bits. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. JMP Near is RIP = RIP + 32-bit offset sign extended to 64-bits.

Pseudo Code

IF condition
	tempEIP = EIP + SignExtend(DEST);
	IF OperandSize = 16
		tempEIP = tempEIP AND 0000FFFFH;
	FI;
	IF tempEIP is not within code segment limit
		#GP(0);
	ELSE
		EIP = tempEIP
	FI;
FI;

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) If the offset being jumped to is beyond the limits of the CS segment.