LAR

Load Access Rights Byte

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F 02 /r LAR r32, r32/m161 A Valid Valid r32  r32/m16 masked by 00FxFF00H
0F 02 /r LAR r16, r16/m16 A Valid Valid r16  r16/m16 masked by FF00H.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (w)

Description

Loads the access rights from the segment descriptor specified by the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. If the source operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-purpose register.

The processor performs access checks as part of the loading process. Once loaded in the destination register, software can perform additional checks on the access rights information.

When the operand size is 32 bits, the access rights for a segment descriptor include the type and DPL fields and the S, P, AVL, D/B, and G flags, all of which are located in the second doubleword (bytes 4 through 7) of the segment descriptor. The double-word is masked by 00FXFF00H before it is loaded into the destination operand. When the operand size is 16 bits, the access rights include the type and DPL fields. Here, the two lower-order bytes of the doubleword are masked by FF00H before being loaded into the destination operand.

This instruction performs the following checks before it loads the access rights in the destination register:

If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.

The LAR instruction can only be executed in protected mode and IA-32e mode.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.W prefix permits access to 64-bit registers as destination.

When the destination operand size is 64 bits, the access rights are loaded from the second doubleword (bytes 4 through 7) of the segment descriptor. The doubleword is masked by 00FXFF00H and zero extended to 64 bits before it is loaded into the destination operand.

Segment and Gate Types
Type Protected Mode IA-32e Mode
Name Valid Name Valid
0 Reserved No Reserved No
1 Available 16-bit TSS Yes Reserved No
2 LDT Yes LDT No
3 Busy 16-bit TSS Yes Reserved No
4 16-bit call gate Yes Reserved No
5 16-bit/32-bit task gate Yes Reserved No
6 16-bit interrupt gate No Reserved No
7 16-bit trap gate No Reserved No
8 Reserved No Reserved No
9 Available 32-bit TSS Yes Available 64-bit TSS Yes
A Reserved No Reserved No
B Busy 32-bit TSS Yes Busy 64-bit TSS Yes
C 32-bit call gate Yes 64-bit call gate Yes
D Reserved No Reserved No
E 32-bit interrupt gate No 64-bit interrupt gate No
F 32-bit trap gate No 64-bit trap gate No

Pseudo Code

IF Offset(SRC) > descriptor table limit
	ZF = 0;
ELSE
	IF SegmentDescriptor(Type) != conforming code segment and (CPL > DPL) or (RPL > DPL) or segment type is not valid for instruction
		ZF = 0
	ELSE
		TEMP = Read segment descriptor ;
		IF OperandSize = 64
			DEST = (ACCESSRIGHTWORD(TEMP) AND 00000000_00FxFF00H);
		ELSE
			(* OperandSize = 32 *)
			DEST = (ACCESSRIGHTWORD(TEMP) AND 00FxFF00H);
		ELSE
			(* OperandSize = 16 *)
			DEST = (ACCESSRIGHTWORD(TEMP) AND FF00H);
		FI;
	FI;
FI;

Flags Affected

The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is set to 0.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory operand effective address is in a non-canonical form.
#SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD The LAR instruction cannot be executed in virtual-8086 mode.

Real-Address Mode Exceptions

Exception Description
#UD The LAR instruction is not recognized in real-address mode.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and the memory operand effec tive address is unaligned while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.