LDDQU

Load Unaligned Integer 128 Bits

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
F2 0F F0 /r LDDQU xmm1, mem A Valid Valid Load unaligned data from mem and return double quadword in xmm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (w)

Description

The instruction is functionally similar to MOVDQU xmm, m128 for loading from memory. That is: 16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 16-byte boundary. Up to 32 bytes may be loaded from memory; this is implementation dependent.

This instruction may improve performance relative to MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by LDDQU be modified and stored to the same location, use MOVDQU or MOVDQA instead of LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the MOVDQA instruction.

Implementation Notes

processor implementation) when the memory address is not aligned on an 8-byte boundary.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

xmm[127:0] = m128;

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and a memory reference is made that is not aligned on an 8-byte boundary. (Generation of this exception depends on processor implementation.)
#PF(fault-code) If a page fault occurs.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and a memory reference is made that is not aligned on an 8-byte boundary. (Generation of this exception depends on processor implementation.)
#PF(fault-code) For a page fault.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and a memory reference is made that is not aligned on an 8-byte boundary. (Generation of this exception depends on processor implementation.)
#UD If CR4.OSFXSR[bit 9] = 0. If CR0.EM[bit 2] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.