MASKMOVQ

Store Selected Bytes of Quadword

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F F7 /r MASKMOVQ mm1, mm2 A Valid Valid Selectively write bytes from mm1 to memory location using the byte mask in mm2. The default memory location is specified by DS:EDI/RDI.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r)

Description

Stores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand (second operand) selects which bytes from the source operand are written to memory. The source and mask operands are MMX technology registers. The location of the first byte of the memory location is specified by DI/EDI and DS registers. (The size of the store address depends on the address-size attribute.)

The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.

The MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-temporal hint is implemented by using a write combining (WC) memory type protocol (see "Caching of Temporal vs. Non-Temporal Data" in Chapter 10, of theIntel®64 and IA-32 Architectures Software Developer'sManual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVQ instructions if multiple processors might use different memory types to read/write the destination memory locations.

This instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]).

The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:

The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-by-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is to be written directly using the byte-mask without allocating old data prior to the store.

In 64-bit mode, the memory address is specified by DS:RDI.

Pseudo Code

IF (MASK[7] = 1)
	DEST[DI/EDI] = SRC[7:0]
ELSE
	(* Memory location unchanged *);
FI;
IF (MASK[15] = 1)
	DEST[DI/EDI +1] = SRC[15:8]
ELSE
	(* Memory location unchanged *);
FI; (* Repeat operation for 3rd through 6th bytes in source operand *)
IF (MASK[63] = 1)
	DEST[DI/EDI +15] = SRC[63:56]
ELSE
	(* Memory location unchanged *);
FI;

Exceptions

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If Mod field of the ModR/M byte not 11B. If the LOCK prefix is used.
#MF If there is a pending FPU exception.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault (implementation specific).
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault (implementation specific).
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#MF If there is a pending FPU exception.
#NM If CR0.TS[bit 3] = 1.
#GP If any part of the operand lies outside the effective address space from 0 to FFFFH. (even if mask is all 0s).

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If Mod field of the ModR/M byte not 11B. If the LOCK prefix is used.
#MF If there is a pending FPU exception.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault (implementation specific).
#SS(0) For an illegal address in the SS segment (even if mask is all 0s).
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments (even if mask is all 0s). If the destination operand is in a nonwritable segment. If the DS, ES, FS, or GS register contains a NULL segment selector.