MOVD/MOVQ

Move Doubleword/Move Quadword

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 6E /r MOVD xmm, r/m32 A Valid Valid Move doubleword from r/m32 to xmm.
REX.W + 0F 7E /r MOVQ r/m64, mm B Valid N.E. Move quadword from mm to r/m64.
0F 7E /r MOVD r/m32, mm B Valid Valid Move doubleword from mm to r/m32.
REX.W + 0F 6E /r MOVQ mm, r/m64 A Valid N.E. Move quadword from r/m64 to mm.
0F 6E /r MOVD mm, r/m32 A Valid Valid Move doubleword from r/m32 to mm.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (w)
B NA NA ModRM:reg (r) ModRM:r/m (w)

Description

Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or 32-bit memory locations. This instruction can be used to move a doubleword to and from the low double-word of an MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot be used to transfer data between MMX technology registers, between XMM registers, between general-purpose registers, or between memory locations.

When the destination operand is an MMX technology register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

(* MOVD instruction when destination operand is MMX technology register *)
DEST[31:0] = SRC;
DEST[63:32] = 00000000H;
(* MOVD instruction when destination operand is XMM register *)
DEST[31:0] = SRC;
DEST[127:32] = 000000000000000000000000H;
MOVD instruction when source operand is MMX technology or XMM register: DEST = SRC[31:0];
(* MOVQ instruction when destination operand is XMM register *)
DEST[63:0] = SRC[63:0];
DEST[127:64] = 0000000000000000H;
MOVQ instruction when destination operand is r/m64: DEST[63:0] = SRC[63:0];
MOVQ instruction when source operand is XMM register or r/m64: DEST = SRC[63:0];

Flags Affected

None. SIMD Floating-Point Exceptions None.

Exceptions

SIMD Floating-Point Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (MMX register operations only) If there is a pending FPU excep tion.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (XMM register operations only) if CR4.OSFXSR[bit 9] = 0. (XMM register operations only) if CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (MMX register operations only) If there is a pending FPU excep tion.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (MMX register operations only) If there is a pending FPU excep tion.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.