MOVMSKPS

Extract Packed Single-Precision Floating-Point Sign Mask

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F 50 /r MOVMSKPS reg, xmm A Valid Valid Extract 4-bit sign mask from xmm and store in reg. The upper bits of r32 or r64 are filled with zeros.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:reg (r) ModRM:reg (w)

Description

Extracts the sign bits from the packed single-precision floating-point values in the source operand (second operand), formats them into a 4-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored in the 4 low-order bits of the destination operand. Zero-extend the upper bits of the destination operand.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode.

Pseudo Code

DEST[0] = SRC[31];
DEST[1] = SRC[63];
DEST[2] = SRC[95];
DEST[3] = SRC[127];
IF DEST = r32
	DEST[31:4] = ZeroExtend;
ELSE
	DEST[63:4] = ZeroExtend;
FI;

Exceptions

SIMD Floating-Point Exceptions

None.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Protected Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.