OR

Logical Inclusive OR

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX.W + 0B /r OR r64, r/m64 D Valid N.E. r64 OR r/m64.
0B /r OR r32, r/m32 D Valid Valid r32 OR r/m32.
0B /r OR r16, r/m16 D Valid Valid r16 OR r/m16.
REX + 0A /r OR r8*, r/m8* D Valid N.E. r8 OR r/m8.
0A /r OR r8, r/m8 D Valid Valid r8 OR r/m8.
REX.W + 09 /r OR r/m64, r64 C Valid N.E. r/m64 OR r64.
09 /r OR r/m32, r32 C Valid Valid r/m32 OR r32.
09 /r OR r/m16, r16 C Valid Valid r/m16 OR r16.
REX + 08 /r OR r/m8*, r8* C Valid N.E. r/m8 OR r8.
08 /r OR r/m8, r8 C Valid Valid r/m8 OR r8.
REX.W + 83 /1 ib OR r/m64, imm8 B Valid N.E. r/m64 OR imm8 (signextended).
83 /1 ib OR r/m32, imm8 B Valid Valid r/m32 OR imm8 (signextended).
83 /1 ib OR r/m16, imm8 B Valid Valid r/m16 OR imm8 (signextended).
REX.W + 81 /1 id OR r/m64, imm32 B Valid N.E. r/m64 OR imm32 (signextended).
81 /1 id OR r/m32, imm32 B Valid Valid r/m32 OR imm32.
81 /1 iw OR r/m16, imm16 B Valid Valid r/m16 OR imm16.
REX + 80 /1 ib OR r/m8*, imm8 B Valid N.E. r/m8 OR imm8.
80 /1 ib OR r/m8, imm8 B Valid Valid r/m8 OR imm8.
REX.W + 0D id OR RAX, imm32 A Valid N.E. RAX OR imm32 (signextended).
0D id OR EAX, imm32 A Valid Valid EAX OR imm32.
0D iw OR AX, imm16 A Valid Valid AX OR imm16.
0C ib OR AL, imm8 A Valid Valid AL OR imm8.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA imm8/16/32 AL/AX/EAX/RAX
B NA NA imm8/16/32 ModRM:r/m (r, w)
C NA NA ModRM:reg (r) ModRM:r/m (r, w)
D NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the first and second operands are 0; otherwise, each bit is set to 1.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

DEST = DEST OR SRC;

Flags Affected

The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.