PCMPEQB/PCMPEQW/PCMPEQD

Compare Packed Data for Equal

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 76 /r PCMPEQD xmm1, xmm2/m128 A Valid Valid Compare packed doublewords in xmm2/m128 and xmm1 for equality.
0F 76 /r PCMPEQD mm, mm/m64 A Valid Valid Compare packed doublewords in mm/m64 and mm for equality.
66 0F 75 /r PCMPEQW xmm1, xmm2/m128 A Valid Valid Compare packed words in xmm2/m128 and xmm1 for equality.
0F 75 /r PCMPEQW mm, mm/m64 A Valid Valid Compare packed words in mm/m64 and mm for equality.
66 0F 74 /r PCMPEQB xmm1, xmm2/m128 A Valid Valid Compare packed bytes in xmm2/m128 and xmm1 for equality.
0F 74 /r PCMPEQB mm, mm/m64 A Valid Valid Compare packed bytes in mm/m64 and mm for equality.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data element in the destination operand is set to all 1s; otherwise, it is set to all 0s. The source operand can be an MMX technology register or a 64-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register.

The PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the PCMPEQW instruction compares the corresponding words in the destination and source operands; and the PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PCMPEQB instruction with 64-bit operands: *)
IF DEST[7:0] = SRC[7:0]
	DEST[7:0) = FFH;
ELSE
	DEST[7:0] = 0;
FI; (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
IF DEST[63:56] = SRC[63:56]
	DEST[63:56] = FFH;
ELSE
	DEST[63:56] = 0;
FI;
(* PCMPEQB instruction with 128-bit operands: *)
IF DEST[7:0] = SRC[7:0]
	DEST[7:0) = FFH;
ELSE
	DEST[7:0] = 0;
FI; (* Continue comparison of 2nd through 15th bytes in DEST and SRC *)
IF DEST[127:120] = SRC[127:120]
	DEST[127:120] = FFH;
ELSE
	DEST[127:120] = 0;
FI;
(* PCMPEQW instruction with 64-bit operands: *)
IF DEST[15:0] = SRC[15:0]
	DEST[15:0] = FFFFH;
ELSE
	DEST[15:0] = 0;
FI; (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
IF DEST[63:48] = SRC[63:48]
	DEST[63:48] = FFFFH;
ELSE
	DEST[63:48] = 0;
FI;
(* PCMPEQW instruction with 128-bit operands: *)
IF DEST[15:0] = SRC[15:0]
	DEST[15:0] = FFFFH;
ELSE
	DEST[15:0] = 0;
FI; (* Continue comparison of 2nd through 7th words in DEST and SRC *)
IF DEST[127:112] = SRC[127:112]
	DEST[127:112] = FFFFH;
ELSE
	DEST[127:112] = 0;
FI;
(* PCMPEQD instruction with 64-bit operands: *)
IF DEST[31:0] = SRC[31:0]
	DEST[31:0] = FFFFFFFFH;
ELSE
	DEST[31:0] = 0;
FI;
IF DEST[63:32] = SRC[63:32]
	DEST[63:32] = FFFFFFFFH;
ELSE
	DEST[63:32] = 0;
FI;
(* PCMPEQD instruction with 128-bit operands: *)
IF DEST[31:0] = SRC[31:0]
	DEST[31:0] = FFFFFFFFH;
ELSE
	DEST[31:0] = 0;
FI; (* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)
IF DEST[127:96] = SRC[127:96]
	DEST[127:96] = FFFFFFFFH;
ELSE
	DEST[127:96] = 0;
FI;

Flags Affected

None.

Exceptions

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.