PEXTRB/PEXTRD/PEXTRQ

Extract Byte/Dword/Qword

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 REX.W 0F 3A 16 /r ib PEXTRQ r/m64, xmm2, imm8 A Valid N. E. Extract a qword integer value from xmm2 at the source qword offset specified by imm8 into r/m64.
66 0F 3A 16 /r ib PEXTRD r/m32, xmm2, imm8 A Valid Valid Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r/m32.
66 0F 3A 14 /r ib PEXTRB reg/m8, xmm2, imm8 A Valid Valid Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into rreg or m8. The upper bits of r32 or r64 are zeroed.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:reg (r) ModRM:r/m (w)

Description

Copies a data element (byte, dword, quadword) in the source operand (second operand) specified by the count operand (third operand) to the destination operand (first operand). The source operand is an XMM register. The destination operand can be a general-purpose register or a memory address. The count operand is an 8-bit immediate. When specifying a quadword [dword, byte] element, the [2, 4] least-significant bit(s) of the count operand specify the location.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15, R8-15). PEXTRQ requires REX.W. If the destination operand is a general-purpose register, the default operand size of PEXTRB/PEXTRW is 64 bits.

Pseudo Code

CASE of
	PEXTRB: SEL = COUNT[3:0];
	TEMP = (Src >> SEL*8) AND FFH;
	IF (DEST = Mem8)
		Mem8 = TEMP[7:0];
	ELSE
		IF (64-Bit Mode and 64-bit register selected)
			R64[7:0] = TEMP[7:0];
			r64[63:8] = ZERO_FILL;
			};
		ELSE
			R32[7:0] = TEMP[7:0];
			r32[31:8] = ZERO_FILL;
			};
		FI;
		PEXTRD:SEL = COUNT[1:0];
		TEMP = (Src >> SEL*32) AND FFFF_FFFFH;
		DEST = TEMP;
		PEXTRQ: SEL = COUNT[0];
		TEMP = (Src >> SEL*64);
		DEST = TEMP;
	FI;
ESAC;

Flags Affected

None

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.