PINSRB/PINSRD/PINSRQ

Insert Byte/Dword/Qword

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 REX.W 0F 3A 22 /r ib PINSRQ xmm1, r/m64, imm8 A N. E. Valid Insert a qword integer value from r/m32 into the xmm1 at the destination element specified by imm8.
66 0F 3A 22 /r ib PINSRD xmm1, r/m32, imm8 A Valid Valid Insert a dword integer value from r/m32 into the xmm1 at the destination element specified by imm8.
66 0F 3A 20 /r ib PINSRB xmm1, r32/m8, imm8 A Valid Valid Insert a byte integer value from r32/m8 into xmm1 at the destination element in xmm1 specified by imm8.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:r/m (r) ModRM:reg (w)

Description

Copies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand (first operand) at the location specified with the count operand (third operand). (The other elements in the destination register are left untouched.) The source operand can be a general-purpose register or a memory location. (When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destination operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte] location in an an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose registers.

Pseudo Code

CASE OF
	PINSRB: SEL = COUNT[3:0];
	MASK = (0FFH << (SEL * 8));
	TEMP = (((SRC[7:0] << (SEL *8)) AND MASK);
	PINSRD: SEL = COUNT[1:0];
	MASK = (0FFFFFFFFH << (SEL * 32));
	TEMP = (((SRC << (SEL *32)) AND MASK) ;
	PINSRQ: SEL = COUNT[0] MASK = (0FFFFFFFFFFFFFFFFH << (SEL * 64));
	TEMP = (((SRC << (SEL *32)) AND MASK) ;
ESAC;
DEST = ((DEST AND NOT MASK) OR TEMP);

Flags Affected

None

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) if any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (Dword and qword references) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.