PMOVMSKB

Move Byte Mask

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F D7 /r PMOVMSKB reg, xmm A Valid Valid Move a byte mask of xmm to reg. The upper bits of r32 or r64 are zeroed
0F D7 /r PMOVMSKB reg, mm A Valid Valid Move a byte mask of mm to reg. The upper bits of r32 or r64 are zeroed

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:reg (r) ModRM:reg (w)

Description

Creates a mask made up of the most significant bit of each byte of the source operand (second operand) and stores the result in the low byte or word of the destination operand (first operand). The source operand is an MMX technology register or an XMM register; the destination operand is a general-purpose register. When operating on 64-bit operands, the byte mask is 8 bits; when operating on 128-bit operands, the byte mask is 16-bits.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode.

Pseudo Code

(* PMOVMSKB instruction with 64-bit source operand and r32: *)
r32[0] = SRC[7];
r32[1] = SRC[15];
(* Repeat operation for bytes 2 through 6 *)
r32[7] = SRC[63];
r32[31:8] = ZERO_FILL;
(* PMOVMSKB instruction with 128-bit source operand and r32: *)
r32[0] = SRC[7];
r32[1] = SRC[15];
(* Repeat operation for bytes 2 through 14 *)
r32[15] = SRC[127];
r32[31:16] = ZERO_FILL;
(* PMOVMSKB instruction with 64-bit source operand and r64: *)
r64[0] = SRC[7];
r64[1] = SRC[15];
(* Repeat operation for bytes 2 through 6 *)
r64[7] = SRC[63];
r64[63:8] = ZERO_FILL;
(* PMOVMSKB instruction with 128-bit source operand and r64: r64[0] = SRC[7]; *)
r64[1] = SRC[15]; (* Repeat operation for bytes 2 through 14 *)
r64[15] = SRC[127];
r64[63:16] = ZERO_FILL;

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Protected Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.