PMOVZX

Packed Move with Zero Extend

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0f 38 35 /r PMOVZXDQ xmm1, xmm2/m64 A Valid Valid Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in xmm1.
66 0f 38 34 /r PMOVZXWQ xmm1, xmm2/m32 A Valid Valid Zero extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1.
66 0f 38 33 /r PMOVZXWD xmm1, xmm2/m64 A Valid Valid Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1.
66 0f 38 32 /r PMOVZXBQ xmm1, xmm2/m16 A Valid Valid Zero extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1.
66 0f 38 31 /r PMOVZXBD xmm1, xmm2/m32 A Valid Valid Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1.
66 0f 38 30 /r PMOVZXBW xmm1, xmm2/m64 A Valid Valid Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (w)

Description

Zero-extend the low byte/word/dword values in each word/dword/qword element of the source operand (second operand) to word/dword/qword integers and stored as packed data in the destination operand (first operand).

Pseudo Code

PMOVZXBW DEST[15:0] = ZeroExtend(SRC[7:0]);
DEST[31:16] = ZeroExtend(SRC[15:8]);
DEST[47:32] = ZeroExtend(SRC[23:16]);
DEST[63:48] = ZeroExtend(SRC[31:24]);
DEST[79:64] = ZeroExtend(SRC[39:32]);
DEST[95:80] = ZeroExtend(SRC[47:40]);
DEST[111:96] = ZeroExtend(SRC[55:48]);
DEST[127:112] = ZeroExtend(SRC[63:56]);
PMOVZXBD DEST[31:0] = ZeroExtend(SRC[7:0]);
DEST[63:32] = ZeroExtend(SRC[15:8]);
DEST[95:64] = ZeroExtend(SRC[23:16]);
DEST[127:96] = ZeroExtend(SRC[31:24]);
PMOVZXQB DEST[63:0] = ZeroExtend(SRC[7:0]);
DEST[127:64] = ZeroExtend(SRC[15:8]);
PMOVZXWD DEST[31:0] = ZeroExtend(SRC[15:0]);
DEST[63:32] = ZeroExtend(SRC[31:16]);
DEST[95:64] = ZeroExtend(SRC[47:32]);
DEST[127:96] = ZeroExtend(SRC[63:48]);
PMOVZXWQ DEST[63:0] = ZeroExtend(SRC[15:0]);
DEST[127:64] = ZeroExtend(SRC[31:16]);
PMOVZXDQ DEST[63:0] = ZeroExtend(SRC[31:0]);
DEST[127:64] = ZeroExtend(SRC[63:32]);

Flags Affected

None

Exceptions

64-Bit Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP if any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.