PMULLW

Multiply Packed Signed Integers and Store Low Result

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F D5 /r PMULLW xmm1, xmm2/m128 A Valid Valid Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of the results in xmm1.
0F D5 /r PMULLW mm, mm/m64 A Valid Valid Multiply the packed signed word integers in mm1 register and mm2/m64, and store the low 16 bits of the results in mm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destination operand. The source operandcan be an MMX technology register or a 64-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PMULLW instruction with 64-bit operands: *)
TEMP0[31:0] = DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] = DEST[31:16] * SRC[31:16];
TEMP2[31:0] = DEST[47:32] * SRC[47:32];
TEMP3[31:0] = DEST[63:48] * SRC[63:48];
DEST[15:0] = TEMP0[15:0];
DEST[31:16] = TEMP1[15:0];
DEST[47:32] = TEMP2[15:0];
DEST[63:48] = TEMP3[15:0];
(* PMULLW instruction with 128-bit operands: *)
TEMP0[31:0] = DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] = DEST[31:16] * SRC[31:16];
TEMP2[31:0] = DEST[47:32] * SRC[47:32];
TEMP3[31:0] = DEST[63:48] * SRC[63:48];
TEMP4[31:0] = DEST[79:64] * SRC[79:64];
TEMP5[31:0] = DEST[95:80] * SRC[95:80];
TEMP6[31:0] = DEST[111:96] * SRC[111:96];
TEMP7[31:0] = DEST[127:112] * SRC[127:112];
DEST[15:0] = TEMP0[15:0];
DEST[31:16] = TEMP1[15:0];
DEST[47:32] = TEMP2[15:0];
DEST[63:48] = TEMP3[15:0];
DEST[79:64] = TEMP4[15:0];
DEST[95:80] = TEMP5[15:0];
DEST[111:96] = TEMP6[15:0];
DEST[127:112] = TEMP7[15:0];

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.