PSHUFB

Packed Shuffle Bytes

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 38 00 /r PSHUFB xmm1, xmm2/m128 A Valid Valid Shuffle bytes in xmm1 according to contents of xmm2/m128.
0F 38 00 /r PSHUFB mm1, mm2/m64 A Valid Valid Shuffle bytes in mm1 according to contents of mm2/m64.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

PSHUFB performs in-place shuffles of bytes in the destination operand (the first operand) according to the shuffle control mask in the source operand (the second operand). The instruction permutes the data in the destination operand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index to permute the corresponding byte in the destination operand. The value of each index is the least significant 4 bits (128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. Both operands can be MMX register or XMM registers. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers.

Pseudo Code

(* PSHUFB with 64 bit operands: *)
for i = 0 to 7 {
if (SRC[(i * 8)+7] = 1) then
DEST[(i*8)+7...(i*8)+0] = 0;
else
index[2..0] = SRC[(i*8)+2 .. (i*8)+0];
DEST[(i*8)+7...(i*8)+0] = DEST[(index*8+7)..(index*8+0)];
endif;
}
(* PSHUFB with 128 bit operands: *)
for i = 0 to 15 { if (SRC[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] = 0;
else index[3..0] = SRC[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] = DEST[(index*8+7)..(index*8+0)];
endif }

Exceptions

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If TS bit in CR0 is set.
#UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. If the LOCK prefix is used.
#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and unaligned memory reference is made while the current privilege level is 3.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If TS bit in CR0 is set.
#UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. If the LOCK prefix is used.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment.