PSRLW/PSRLD/PSRLQ

Shift Packed Data Right Logical

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 73 /2 ib PSRLQ xmm1, imm8 B Valid Valid Shift quadwords in xmm1 right by imm8 while shifting in 0s.
0F 73 /2 ib PSRLQ mm, imm8 B Valid Valid Shift mm right by imm8 while shifting in 0s.
66 0F D3 /r PSRLQ xmm1, xmm2/m128 A Valid Valid Shift quadwords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.
0F D3 /r PSRLQ mm, mm/m64 A Valid Valid Shift mm right by amount specified in mm/m64 while shifting in 0s.
66 0F 72 /2 ib PSRLD xmm1, imm8 B Valid Valid Shift doublewords in xmm1 right by imm8 while shifting in 0s.
0F 72 /2 ib PSRLD mm, imm8 B Valid Valid Shift doublewords in mm right by imm8 while shifting in 0s.
66 0F D2 /r PSRLD xmm1, xmm2/m128 A Valid Valid Shift doublewords in xmm1 right by amount specified in xmm2 /m128 while shifting in 0s.
0F D2 /r PSRLD mm, mm/m64 A Valid Valid Shift doublewords in mm right by amount specified in mm/m64 while shifting in 0s.
66 0F 71 /2 ib PSRLW xmm1, imm8 B Valid Valid Shift words in xmm1 right by imm8 while shifting in 0s.
0F 71 /2 ib PSRLW mm, imm8 B Valid Valid Shift words in mm right by imm8 while shifting in 0s.
66 0F D1 /r PSRLW xmm1, xmm2/m128 A Valid Valid Shift words in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.
0F D1 /r PSRLW mm, mm/m64 A Valid Valid Shift words in mm right by amount specified in mm/m64 while shifting in 0s.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)
B NA NA imm8 ModRM:r/m (r, w)

Description

Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s.

The destination operand may be an MMX technology register or an XMM register; the count operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note that only the first 64-bits of a 128-bit count operand are checked to compute the count.

The PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits specified in the count operand; the PSRLD instruction shifts each of the doublewords in the destination operand; and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PSRLW instruction with 64-bit operand: *)
IF (COUNT > 15)
	DEST[64:0] = 0000000000000000H
ELSE
	DEST[15:0] = ZeroExtend(DEST[15:0] >> COUNT); (* Repeat shift operation for 2nd and 3rd words *)
	DEST[63:48] = ZeroExtend(DEST[63:48] >> COUNT);
FI;
(* PSRLD instruction with 64-bit operand: *)
IF (COUNT > 31)
	DEST[64:0] = 0000000000000000H
ELSE
	DEST[31:0] = ZeroExtend(DEST[31:0] >> COUNT);
	DEST[63:32] = ZeroExtend(DEST[63:32] >> COUNT);
FI;
(* PSRLQ instruction with 64-bit operand: *)
IF (COUNT > 63)
	DEST[64:0] = 0000000000000000H
ELSE
	DEST = ZeroExtend(DEST >> COUNT);
FI;
(* PSRLW instruction with 128-bit operand: COUNT = COUNT_SOURCE[63:0]; *)
IF (COUNT > 15)
	DEST[128:0] = 00000000000000000000000000000000H
ELSE
	DEST[15:0] = ZeroExtend(DEST[15:0] >> COUNT); (* Repeat shift operation for 2nd through 7th words *)
	DEST[127:112] = ZeroExtend(DEST[127:112] >> COUNT);
FI;
(* PSRLD instruction with 128-bit operand: COUNT = COUNT_SOURCE[63:0]; *)
IF (COUNT > 31)
	DEST[128:0] = 00000000000000000000000000000000H
ELSE
	DEST[31:0] = ZeroExtend(DEST[31:0] >> COUNT); (* Repeat shift operation for 2nd and 3rd doublewords *)
	DEST[127:96] = ZeroExtend(DEST[127:96] >> COUNT);
FI;
(* PSRLQ instruction with 128-bit operand: *)
COUNT = COUNT_SOURCE[63:0];
IF (COUNT > 15)
	DEST[128:0] = 00000000000000000000000000000000H
ELSE
	DEST[63:0] = ZeroExtend(DEST[63:0] >> COUNT);
	DEST[127:64] = ZeroExtend(DEST[127:64] >> COUNT);
FI;

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Compatibility Mode Exceptions

Exception Description
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.