PSUBB/PSUBW/PSUBD

Subtract Packed Integers

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F FA /r PSUBD xmm1, xmm2/m128 A Valid Valid Subtract packed doubleword integers in xmm2/mem128 from packed doubleword integers in xmm1.
0F FA /r PSUBD mm, mm/m64 A Valid Valid Subtract packed doubleword integers in mm/m64 from packed doubleword integers in mm.
66 0F F9 /r PSUBW xmm1, xmm2/m128 A Valid Valid Subtract packed word integers in xmm2/m128 from packed word integers in xmm1.
0F F9 /r PSUBW mm, mm/m64 A Valid Valid Subtract packed word integers in mm/m64 from packed word integers in mm.
66 0F F8 /r PSUBB xmm1, xmm2/m128 A Valid Valid Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1.
0F F8 /r PSUBB mm, mm/m64 A Valid Valid Subtract packed byte integers in mm/m64 from packed byte integers in mm.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers of the destination operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the IntelĀ® 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.

These instructions can operate on either 64-bit or 128-bit operands. When operating on 64-bit operands, the destination operand must be an MMX technology register and the source operand can be either an MMX technology register or a 64-bit memory location. When operating on 128-bit operands, the destination operand must be an XMM register and the source operand can be either an XMM register or a 128-bit memory location.

The PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be represented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.

The PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.

The PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination element.

Note that the PSUBB, PSUBW, and PSUBD instructions can operate on either unsigned or signed (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which it operates.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PSUBB instruction with 64-bit operands: DEST[7:0] = DEST[7:0] - SRC[7:0]; (* Repeat subtract operation for 2nd through 7th byte *) *)
DEST[63:56] = DEST[63:56] - SRC[63:56];
(* PSUBB instruction with 128-bit operands: DEST[7:0] = DEST[7:0] - SRC[7:0]; (* Repeat subtract operation for 2nd through 14th byte *) *)
DEST[127:120] = DEST[111:120] - SRC[127:120];
(* PSUBW instruction with 64-bit operands: DEST[15:0] = DEST[15:0] - SRC[15:0]; (* Repeat subtract operation for 2nd and 3rd word *) *)
DEST[63:48] = DEST[63:48] - SRC[63:48];
(* PSUBW instruction with 128-bit operands: DEST[15:0] = DEST[15:0] - SRC[15:0]; (* Repeat subtract operation for 2nd through 7th word *) *)
DEST[127:112] = DEST[127:112] - SRC[127:112];
(* PSUBD instruction with 64-bit operands: DEST[31:0] = DEST[31:0] - SRC[31:0]; *)
DEST[63:32] = DEST[63:32] - SRC[63:32];
(* PSUBD instruction with 128-bit operands: DEST[31:0] = DEST[31:0] - SRC[31:0]; (* Repeat subtract operation for 2nd and 3rd doubleword *) *)
DEST[127:96] = DEST[127:96] - SRC[127:96];

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.