PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ

Unpack Low Data

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 6C /r PUNPCKLQDQ xmm1, xmm2/m128 A Valid Valid Interleave low-order quadword from xmm1 and xmm2/m128 into xmm1 register.
66 0F 62 /r PUNPCKLDQ xmm1, xmm2/m128 A Valid Valid Interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1.
0F 62 /r PUNPCKLDQ mm, mm/m32 A Valid Valid Interleave low-order doublewords from mm and mm/m32 into mm.
66 0F 61 /r PUNPCKLWD xmm1, xmm2/m128 A Valid Valid Interleave low-order words from xmm1 and xmm2/m128 into xmm1.
0F 61 /r PUNPCKLWD mm, mm/m32 A Valid Valid Interleave low-order words from mm and mm/m32 into mm.
66 0F 60 /r PUNPCKLBW xmm1, xmm2/m128 A Valid Valid Interleave low-order bytes from xmm1 and xmm2/m128 into xmm1.
0F 60 /r PUNPCKLBW mm, mm/m32 A Valid Valid Interleave low-order bytes from mm and mm/m32 into mm.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destination operand (first operand) and source operand (second operand) into the destination operand. The high-order data elements are ignored.

The source operand can be an MMX technology register or a 32-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register. When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.

The PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination operands, and the PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination operands.

These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data elements from the original value in the destination operand. For example, with the PUNPCKLBW instruction the high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the PUNPCKLWD instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PUNPCKLBW instruction with 64-bit operands: *)
DEST[63:56] = SRC[31:24];
DEST[55:48] = DEST[31:24];
DEST[47:40] = SRC[23:16];
DEST[39:32] = DEST[23:16];
DEST[31:24] = SRC[15:8];
DEST[23:16] = DEST[15:8];
DEST[15:8] = SRC[7:0];
DEST[7:0] = DEST[7:0];
(* PUNPCKLWD instruction with 64-bit operands: DEST[63:48] = SRC[31:16]; *)
DEST[47:32] = DEST[31:16];
DEST[31:16] = SRC[15:0];
DEST[15:0] = DEST[15:0];
(* PUNPCKLDQ instruction with 64-bit operands: DEST[63:32] = SRC[31:0]; *)
DEST[31:0] = DEST[31:0];
(* PUNPCKLBW instruction with 128-bit operands: DEST[7:0] = DEST[7:0]; *)
DEST[15:8] = SRC[7:0];
DEST[23:16] = DEST[15:8];
DEST[31:24] = SRC[15:8];
DEST[39:32] = DEST[23:16];
DEST[47:40] = SRC[23:16];
DEST[55:48] = DEST[31:24];
DEST[63:56] = SRC[31:24];
DEST[71:64] = DEST[39:32];
DEST[79:72] = SRC[39:32];
DEST[87:80] = DEST[47:40];
DEST[95:88] = SRC[47:40];
DEST[103:96] = DEST[55:48];
DEST[111:104] = SRC[55:48];
DEST[119:112] = DEST[63:56];
DEST[127:120] = SRC[63:56];
(* PUNPCKLWD instruction with 128-bit operands: DEST[15:0] = DEST[15:0]; *)
DEST[31:16] = SRC[15:0];
DEST[47:32] = DEST[31:16];
DEST[63:48] = SRC[31:16];
DEST[79:64] = DEST[47:32];
DEST[95:80] = SRC[47:32];
DEST[111:96] = DEST[63:48];
DEST[127:112] = SRC[63:48];
(* PUNPCKLDQ instruction with 128-bit operands: DEST[31:0] = DEST[31:0]; *)
DEST[63:32] = SRC[31:0];
DEST[95:64] = DEST[63:32];
DEST[127:96] = SRC[63:32];
PUNPCKLQDQ DEST[63:0] = DEST[63:0];
DEST[127:64] = SRC[63:0];

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0) If the memory address is in a non-canonical form. (128-bit version only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions (except PUNPCKLQDQ) on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. (PUNPCKLQDQ only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Protected Mode Exceptions

Exception Description
#AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions (PUNPCKLQDQ) on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. (PUNPCKLQDQ only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.