RCL/RCR/ROL/ROR

Perform bit rotation

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX + D0 /3 RCR r/m8*, 1 A Valid N.E. Rotate 9 bits (CF, r/m8) right once.
D0 /3 RCR r/m8, 1 A Valid Valid Rotate 9 bits (CF, r/m8) right once.
REX.W + C1 /2 ib RCL r/m64, imm8 C Valid N.E. Rotate 65 bits (CF, r/m64) left imm8 times. Uses a 6 bit count.
C1 /2 ib RCL r/m32, imm8 C Valid Valid Rotate 33 bits (CF, r/m32) left imm8 times.
REX.W + D3 /2 RCL r/m64, CL B Valid N.E. Rotate 65 bits (CF, r/m64) left CL times. Uses a 6 bit count.
D3 /2 RCL r/m32, CL B Valid Valid Rotate 33 bits (CF, r/m32) left CL times.
REX.W + D1 /2 RCL r/m64, 1 A Valid N.E. Rotate 65 bits (CF, r/m64) left once. Uses a 6 bit count.
D1 /2 RCL r/m32, 1 A Valid Valid Rotate 33 bits (CF, r/m32) left once.
C1 /2 ib RCL r/m16, imm8 C Valid Valid Rotate 17 bits (CF, r/m16) left imm8 times.
D3 /2 RCL r/m16, CL B Valid Valid Rotate 17 bits (CF, r/m16) left CL times.
D1 /2 RCL r/m16, 1 A Valid Valid Rotate 17 bits (CF, r/m16) left once.
REX + C0 /2 ib RCL r/m8*, imm8 C Valid N.E. Rotate 9 bits (CF, r/m8) left imm8 times.
C0 /2 ib RCL r/m8, imm8 C Valid Valid Rotate 9 bits (CF, r/m8) left imm8 times.
REX + D2 /2 RCL r/m8*, CL B Valid N.E. Rotate 9 bits (CF, r/m8) left CL times.
D2 /2 RCL r/m8, CL B Valid Valid Rotate 9 bits (CF, r/m8) left CL times.
REX + D0 /2 RCL r/m8*, 1 A Valid N.E. Rotate 9 bits (CF, r/m8) left once.
D0 /2 RCL r/m8, 1 A Valid Valid Rotate 9 bits (CF, r/m8) left once.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA 1 ModRM:r/m (w)
B NA NA CL (r) ModRM:r/m (w)
C NA NA imm8 ModRM:r/m (w)

Description

Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31 by masking all the bits in the count operand except the 5 least-significant bits.

The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except for the least-significant bit, which is rotated to the most-significant bit location.

The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into the most-significant bit and shifts the least-significant bit into the CF flag. For the ROL and ROR instructions, the original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.

The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except that a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the exclusive OR of the two most-significant bits of the result.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Use of REX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.

Pseudo Code

(* RCL and RCR instructions *)
SIZE = OperandSize;
CASE (determine count) OF
	SIZE = 8:
	tempCOUNT = (COUNT AND 1FH) MOD 9;
	SIZE = 16:
	tempCOUNT = (COUNT AND 1FH) MOD 17;
	SIZE = 32:
	tempCOUNT = COUNT AND 1FH;
	SIZE = 64:
	tempCOUNT = COUNT AND 3FH;
ESAC;
(* RCL instruction operation *)
WHILE (tempCOUNT != 0)
	tempCF = MSB(DEST);
	DEST = (DEST * 2) + CF;
	CF = tempCF;
	tempCOUNT = tempCOUNT - 1;
ELIHW;
IF COUNT = 1
	OF = MSB(DEST) XOR CF;
ELSE
	OF is undefined;
FI;
(* RCR instruction operation *)
IF COUNT = 1
	OF = MSB(DEST) XOR CF;
ELSE
	OF is undefined;
FI;
WHILE (tempCOUNT != 0)
	DO tempCF = LSB(SRC);
	DEST = (DEST / 2) + (CF * pow(2, SIZE);
	CF = tempCF;
	tempCOUNT = tempCOUNT - 1;
ELIHW;
(* ROL and ROR instructions *)
SIZE = OperandSize;
CASE (determine count) OF
	SIZE = 8:
	tempCOUNT = (COUNT AND 1FH) MOD 8; (* Mask count before MOD *)
	SIZE = 16:
	tempCOUNT = (COUNT AND 1FH) MOD 16;
	SIZE = 32:
	tempCOUNT = (COUNT AND 1FH) MOD 32;
	SIZE = 64:
	tempCOUNT = (COUNT AND 3FH) MOD 64;
ESAC;
(* ROL instruction operation *)
IF (tempCOUNT > 0) (* Prevents updates to CF *)
	WHILE (tempCOUNT != 0)
		DO tempCF = MSB(DEST);
		DEST = (DEST * 2) + tempCF;
		tempCOUNT = tempCOUNT - 1;
	ELIHW;
	CF = LSB(DEST);
	IF COUNT = 1
		OF = MSB(DEST) XOR CF;
	ELSE
		OF is undefined;
	FI;
FI;
(* ROR instruction operation *)
IF tempCOUNT > 0) (* Prevent updates to CF *)
	WHILE (tempCOUNT != 0)
		DO tempCF = LSB(SRC);
		DEST = (DEST / 2) + (tempCF * pow(2, SIZE);
		tempCOUNT = tempCOUNT - 1;
	ELIHW;
	CF = MSB(DEST);
	IF COUNT = 1
		OF = MSB(DEST) XOR MSB - 1(DEST);
	ELSE
		OF is undefined;
	FI;
FI;

Flags Affected

The CF flag contains the value of the bit shifted into it. The OF flag is affected only for single-bit rotates (see "Description" above); it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the source operand is located in a nonwritable segment. If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the source operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.