ROUNDPS

Round Packed Single Precision Floating-Point Values

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
66 0F 3A 08 /r ib ROUNDPS xmm1, xmm2/m128, imm8 A Valid Valid Round packed single precision floating-point values in xmm2/m128 and place the result in xmm1. The rounding mode is determined by imm8.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:r/m (r) ModRM:reg (w)

Description

Round the 4 single-precision floating-point values in the source operand (second operand) using the rounding mode specified in the immediate operand (third operand) and place the results in the destination operand (first operand). The rounding process rounds each input floating-point value to an integer value and returns the integer result as a single-precision floating-point value.

The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in Figure 4-14. Bit 3 of the immediate byte controlsprocessor behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-14 lists theencoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ' then denormals will be converted to zero before rounding.

Pseudo Code

IF (imm[2] = ')
	(* rounding mode is determined by MXCSR.RC *)
	DEST[31:0] = ConvertSPFPToInteger_M(SRC[31:0]);
	DEST[63:32] = ConvertSPFPToInteger_M(SRC[63:32]);
	DEST[95:64] = ConvertSPFPToInteger_M(SRC[95:64]);
	DEST[127:96] = ConvertSPFPToInteger_M(SRC[127:96]);
ELSE
	(* rounding mode is determined by IMM8.RC *)
	DEST[31:0] = ConvertSPFPToInteger_Imm(SRC[31:0]);
	DEST[63:32] = ConvertSPFPToInteger_Imm(SRC[63:32]);
	DEST[95:64] = ConvertSPFPToInteger_Imm(SRC[95:64]);
	DEST[127:96] = ConvertSPFPToInteger_Imm(SRC[127:96]);
FI;

Exceptions

SIMD Floating-Point Exceptions

Invalid (signaled only if SRC = SNaN) Precision (signaled only if imm[3] = ‘0; if imm[3] = ', then the Precision Mask in the MXSCSR is ignored and precision exception is not signaled.) Note that Denormal is not signaled by ROUNDPS.

64-Bit Mode Exceptions

Exception Description
#UD If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag ECX.SSE4_1 is 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If TS in CR0 is set.
#PF(fault-code) For a page fault.
#SS(0) If a memory address referencing the SS segment is in a non- canonical form.
#GP(0) If the memory address is in a non-canonical form. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in Real Address Mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#GP(0) if any part of the operand lies outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.

Protected Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE4_1[bit 19] = 0. If LOCK prefix is used. Either the prefix REP (F3h) or REPN (F2H) is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.