SHUFPS

Shuffle Packed Single-Precision Floating-Point Values

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F C6 /r ib SHUFPS xmm1, xmm2/m128, imm8 A Valid Valid Shuffle packed singleprecision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA imm8 ModRM:r/m (r) ModRM:reg (r, w)

Description

Moves two of the four packed single-precision floating-point values from the destination operand (first operand) into the low quadword of the destination operand; moves two of the four packed single-precision floating-point values from the source operand (second operand) into to the high quadword of the destination operand. The select operand (third operand) determines which values aremoved to the destination operand.

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The select operand is an 8-bit immediate: bits 0 and 1 select the value to be moved from the destination operand to the low double-word of the result, bits 2 and 3 select the value to be moved from the destination operand to the second doubleword of the result, bits 4 and 5 select the value to be moved from the source operand to the third doubleword of the result, and bits 6 and 7 select the value to be moved from the source operand to the high doubleword of the result.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

CASE (SELECT[1:0]) OF
	0: DEST[31:0] = DEST[31:0];
	1: DEST[31:0] = DEST[63:32];
	2: DEST[31:0] = DEST[95:64];
	3: DEST[31:0] = DEST[127:96];
ESAC;
CASE (SELECT[3:2]) OF
	0: DEST[63:32] = DEST[31:0];
	1: DEST[63:32] = DEST[63:32];
	2: DEST[63:32] = DEST[95:64];
	3: DEST[63:32] = DEST[127:96];
ESAC;
CASE (SELECT[5:4]) OF
	0: DEST[95:64] = SRC[31:0];
	1: DEST[95:64] = SRC[63:32];
	2: DEST[95:64] = SRC[95:64];
	3: DEST[95:64] = SRC[127:96];
ESAC;
CASE (SELECT[7:6]) OF
	0: DEST[127:96] = SRC[31:0];
	1: DEST[127:96] = SRC[63:32];
	2: DEST[127:96] = SRC[95:64];
	3: DEST[127:96] = SRC[127:96];
ESAC;

Exceptions

SIMD Floating-Point Exceptions

None.

64-Bit Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#GP(0) If memory operand is not aligned on a 16-byte boundary, regardless of segment. If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#PF(fault-code) For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception Description
#UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) For a page fault.
#SS(0) For an illegal address in the SS segment.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.