SUB

Subtract

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
81 /5 id SUB r/m32, imm32 B Valid Valid Subtract imm32 from r/m32.
81 /5 iw SUB r/m16, imm16 B Valid Valid Subtract imm16 from r/m16.
REX + 80 /5 ib SUB r/m8*, imm8 B Valid N.E. Subtract imm8 from r/m8.
80 /5 ib SUB r/m8, imm8 B Valid Valid Subtract imm8 from r/m8.
REX.W + 2D id SUB RAX, imm32 A Valid N.E. Subtract imm32 sign-extended to 64-bits from RAX.
2D id SUB EAX, imm32 A Valid Valid Subtract imm32 from EAX.
2D iw SUB AX, imm16 A Valid Valid Subtract imm16 from AX.
2C ib SUB AL, imm8 A Valid Valid Subtract imm8 from AL.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA imm8/26/32 AL/AX/EAX/RAX
B NA NA imm8/26/32 ModRM:r/m (r, w)
C NA NA ModRM:reg (r) ModRM:r/m (r, w)
D NA NA ModRM:r/m (r) ModRM:reg (r, w)

Description

Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, register, or memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The SUB instruction performs integer subtraction. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate an overflow in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

Pseudo Code

DEST = (DEST - SRC);

Flags Affected

The OF, SF, ZF, AF, PF, and CF flags are set according to the result.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used but the destination is not a memory operand.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.