TEST

Logical Compare

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
REX.W + 85 /r TEST r/m64, r64 C Valid N.E. AND r64 with r/m64; set SF, ZF, PF according to result.
85 /r TEST r/m32, r32 C Valid Valid AND r32 with r/m32; set SF, ZF, PF according to result.
85 /r TEST r/m16, r16 C Valid Valid AND r16 with r/m16; set SF, ZF, PF according to result.
REX + 84 /r TEST r/m8*, r8* C Valid N.E. AND r8 with r/m8; set SF, ZF, PF according to result.
84 /r TEST r/m8, r8 C Valid Valid AND r8 with r/m8; set SF, ZF, PF according to result.
REX.W + F7 /0 id TEST r/m64, imm32 B Valid N.E. AND imm32 sign-extended to 64-bits with r/m64; set SF, ZF, PF according to result.
F7 /0 id TEST r/m32, imm32 B Valid Valid AND imm32 with r/m32; set SF, ZF, PF according to result.
F7 /0 iw TEST r/m16, imm16 B Valid Valid AND imm16 with r/m16; set SF, ZF, PF according to result.
REX + F6 /0 ib TEST r/m8*, imm8 B Valid N.E. AND imm8 with r/m8; set SF, ZF, PF according to result.
F6 /0 ib TEST r/m8, imm8 B Valid Valid AND imm8 with r/m8; set SF, ZF, PF according to result.
REX.W + A9 id TEST RAX, imm32 A Valid N.E. AND imm32 sign-extended to 64-bits with RAX; set SF, ZF, PF according to result.
A9 id TEST EAX, imm32 A Valid Valid AND imm32 with EAX; set SF, ZF, PF according to result.
A9 iw TEST AX, imm16 A Valid Valid AND imm16 with AX; set SF, ZF, PF according to result.
A8 ib TEST AL, imm8 A Valid Valid AND imm8 with AL; set SF, ZF, PF according to result.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA imm8/16/32 AL/AX/EAX/RAX
B NA NA imm8/16/32 ModRM:r/m (r)
C NA NA ModRM:reg (r) ModRM:r/m (r)

Description

Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Pseudo Code

TEMP = SRC1 AND SRC2;
SF = MSB(TEMP);
IF TEMP = 0
	ZF = 1;
ELSE
	ZF = 0;
FI;
PF = BitwiseXNOR(TEMP[0:7]);
CF = 0;
OF = 0;
(* AF is undefined *)

Flags Affected

The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the "Operation" section above). The state of the AF flag is undefined.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#SS If a memory operand effective address is outside the SS segment limit.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.