VERR/VERW

Verify a Segment for Reading or Writing

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F 00 /5 VERW r/m16 B Valid Valid Set ZF=1 if segment specified with r/m16 can be written.
0F 00 /4 VERR r/m16 A Valid Valid Set ZF=1 if segment specified with r/m16 can be read.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA NA ModRM:r/m (r)
B NA NA NA NA

Description

Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable. This check cannot be performed on system segments.

To set the ZF flag, the following conditions must be met:

The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a protection exception, enabling the software to anticipate possible segment access problems.

This instruction's operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.

Pseudo Code

IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
	ZF = 0;
FI;
Read segment descriptor;
IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
	or (SegmentDescriptor(Type) != conforming code segment) and (CPL > DPL) or (RPL > DPL)
	ZF = 0;
ELSE
	IF ((Instruction = VERR) and (Segment readable)) or ((Instruction = VERW) and (Segment writable))
		ZF = 1;
	FI;
FI;

Flags Affected

The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.

Exceptions

64-Bit Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#GP(0) If the memory address is in a non-canonical form.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#UD The VERR and VERW instructions are not recognized in virtual8086 mode. If the LOCK prefix is used.

Real-Address Mode Exceptions

Exception Description
#UD The VERR and VERW instructions are not recognized in real-address mode. If the LOCK prefix is used.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code) If a page fault occurs.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
The only exceptions generated for these instructions are those related to illegal addressing of the source operand.