WRMSR

Write to Model Specific Register

Opcodes

Hex Mnemonic Encoding Long Mode Legacy Mode Description
0F 30 WRMSR A Valid Valid Write the value in EDX:EAX to MSR specified by ECX.

Instruction Operand Encoding

Op/En Operand 0 Operand 1 Operand 2 Operand 3
A NA NA NA NA

Description

Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously read.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to bits in a reserved MSR.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated.This includes global entries (see "Translation Lookaside Buffers (TLBs)" in Chapter 3of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A).

MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Appendix B, "Model-Specific Registers (MSRs)", in theIntel®64 and IA-32 Architectures Software Developer's Manual, Volume 3B, lists all MSRs that can be read with this instruction and their addresses. Note that each processor family has its own set of MSRs.

The WRMSR instruction is a serializing instruction (see "Serializing Instructions" in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer's Manual,Volume 3A).

The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.

Pseudo Code

MSR[ECX] = EDX:EAX;

Flags Affected

None.

Exceptions

64-Bit Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception Description
#GP(0) The WRMSR instruction is not recognized in virtual-8086 mode.

Real-Address Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP If the value in ECX specifies a reserved or unimplemented MSR address. If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.

Protected Mode Exceptions

Exception Description
#UD If the LOCK prefix is used.
#GP(0) If the current privilege level is not 0. If the value in ECX specifies a reserved or unimplemented MSR address. If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.